targets: Remove int() on BaseSoC's sys_clk_freq.

litex_boards/targets/adi_adrv2crr_fmc.py

@@ -61,7 +61,7 @@ class CRG(LiteXModule):
 # BaseSoC -----------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(150e6), ddram_channel=0, with_led_chaser=True,
+    def __init__(self, sys_clk_freq=150e6, ddram_channel=0, with_led_chaser=True,
                  with_pcie=False, **kwargs):
         platform = adi_adrv2crr_fmc.Platform()
 

litex_boards/targets/adi_plutosdr.py

@@ -57,7 +57,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
+    def __init__(self, sys_clk_freq=100e6, **kwargs):
         platform = adi_plutosdr.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/alchitry_au.py

@@ -50,7 +50,7 @@ class CRG(LiteXModule):
 # BaseSoC -----------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, variant="au", sys_clk_freq=int(83333333), with_spi_flash=False, with_led_chaser=True, **kwargs):
+    def __init__(self, variant="au", sys_clk_freq=83.333e6, with_spi_flash=False, with_led_chaser=True, **kwargs):
         platform = alchitry_au.Platform(variant=variant)
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/alchitry_mojo.py

@@ -92,7 +92,7 @@ class CRG(LiteXModule):
 # BaseSoC -----------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(62.5e6), sdram_rate="1:1", with_hdmi_shield=False,
+    def __init__(self, sys_clk_freq=62.5e6, sdram_rate="1:1", with_hdmi_shield=False,
                  with_sdram_shield=False, with_led_chaser=True, with_video_terminal=False,
                  with_video_framebuffer=False, with_video_colorbars=False, **kwargs):
         platform = alchitry_mojo.Platform()

litex_boards/targets/aliexpress_xc7k420t.py

@@ -39,7 +39,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, with_spi_flash=False, **kwargs):
+    def __init__(self, sys_clk_freq=100e6, with_led_chaser=True, with_spi_flash=False, **kwargs):
         platform = aliexpress_xc7k420t.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/alinx_ax7010.py

@@ -36,7 +36,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, **kwargs):
+    def __init__(self, sys_clk_freq=100e6, with_led_chaser=True, **kwargs):
         platform = alinx_ax7010.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/alinx_axu2cga.py

@@ -66,7 +66,7 @@ class _CRG(LiteXModule):
 
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(25e6), with_led_chaser=True, **kwargs):
+    def __init__(self, sys_clk_freq=25e6, with_led_chaser=True, **kwargs):
         platform = alinx_axu2cga.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/antmicro_artix_dc_scm.py

@@ -63,7 +63,7 @@ class _CRG(LiteXModule):
 
 class BaseSoC(SoCCore):
     def __init__(self, *, device, with_pcie, with_etherbone, with_ethernet, with_sdram, eth_dynamic_ip,
-            eth_reset_time, toolchain="vivado", sys_clk_freq=int(100e6), eth_ip="192.168.1.120", **kwargs):
+            eth_reset_time, toolchain="vivado", sys_clk_freq=100e6, eth_ip="192.168.1.120", **kwargs):
         platform = antmicro_artix_dc_scm.Platform(device=device, toolchain=toolchain)
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/antmicro_datacenter_ddr4_test_board.py

@@ -74,7 +74,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, *, sys_clk_freq=int(100e6), iodelay_clk_freq=200e6,
+    def __init__(self, *, sys_clk_freq=100e6, iodelay_clk_freq=200e6,
             with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_reset_time="10e-3", eth_dynamic_ip=False,
             with_hyperram=False, with_sdcard=False, with_jtagbone=True, with_uartbone=False, with_spi_flash=False,
             with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False, **kwargs):

litex_boards/targets/antmicro_lpddr4_test_board.py

@@ -46,7 +46,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, *, sys_clk_freq=int(50e6), iodelay_clk_freq=200e6,
+    def __init__(self, *, sys_clk_freq=50e6, iodelay_clk_freq=200e6,
             with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
             with_hyperram=False, with_sdcard=False, with_jtagbone=True, with_uartbone=False,
             with_led_chaser=True, **kwargs):

litex_boards/targets/arduino_mkrvidor4000.py

@@ -48,7 +48,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(48e6), **kwargs):
+    def __init__(self, sys_clk_freq=48e6, **kwargs):
         platform = arduino_mkrvidor4000.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/avnet_aesku40.py

@@ -58,7 +58,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_etherbone=False,
+    def __init__(self, sys_clk_freq=125e6, with_ethernet=False, with_etherbone=False,
                  eth_ip="192.168.1.50", with_led_chaser=True, with_pcie=False, with_sata=False,
                  **kwargs):
         platform = avnet_aesku40.Platform()

litex_boards/targets/berkeleylab_marble.py

@@ -69,7 +69,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(125e6),
+    def __init__(self, sys_clk_freq=125e6,
         with_ethernet   = False,
         with_etherbone  = False,
         with_rts_reset  = False,

litex_boards/targets/camlink_4k.py

@@ -69,9 +69,9 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, toolchain="trellis", with_led_chaser=True, **kwargs):
+    def __init__(self, sys_clk_freq=81e6, toolchain="trellis", with_led_chaser=True, **kwargs):
         platform = camlink_4k.Platform(toolchain=toolchain)
-        sys_clk_freq = int(81e6)
+
 
         # CRG --------------------------------------------------------------------------------------
         self.crg = _CRG(platform, sys_clk_freq)

litex_boards/targets/decklink_intensity_pro_4k.py

@@ -41,7 +41,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, **kwargs):
+    def __init__(self, sys_clk_freq=125e6, with_pcie=False, **kwargs):
         platform = decklink_intensity_pro_4k.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/decklink_mini_4k.py

@@ -72,7 +72,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCMini):
-    def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, with_sata=False, with_video_terminal=False, with_video_framebuffer=False, **kwargs):
+    def __init__(self, sys_clk_freq=100e6, with_pcie=False, with_sata=False, with_video_terminal=False, with_video_framebuffer=False, **kwargs):
         if with_video_terminal or with_video_framebuffer:
             sys_clk_freq = int(148.5e6) # FIXME: For now requires sys_clk >= video_clk.
         platform = decklink_mini_4k.Platform()

litex_boards/targets/decklink_quad_hdmi_recorder.py

@@ -60,7 +60,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(200e6), with_pcie=False, pcie_lanes=4, **kwargs):
+    def __init__(self, sys_clk_freq=200e6, with_pcie=False, pcie_lanes=4, **kwargs):
         platform = decklink_quad_hdmi_recorder.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/digilent_arty.py

@@ -70,7 +70,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, variant="a7-35", toolchain="vivado", sys_clk_freq=int(100e6),
+    def __init__(self, variant="a7-35", toolchain="vivado", sys_clk_freq=100e6,
         with_ethernet   = False,
         with_etherbone  = False,
         eth_ip          = "192.168.1.50",
@@ -156,8 +156,8 @@ class BaseSoC(SoCCore):
 def main():
     from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=digilent_arty.Platform, description="LiteX SoC on Arty A7.")
-    parser.add_target_argument("--flash",      , action="store_true",       help="Flash bitstream.")
-    parser.add_target_argument("--variant",    , default="a7-35",           help="Board variant (a7-35 or a7-100).")
+    parser.add_target_argument("--flash",        action="store_true",       help="Flash bitstream.")
+    parser.add_target_argument("--variant",      default="a7-35",           help="Board variant (a7-35 or a7-100).")
     parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
     ethopts = parser.target_group.add_mutually_exclusive_group()
     ethopts.add_argument("--with-ethernet",        action="store_true",    help="Enable Ethernet support.")

litex_boards/targets/digilent_arty_s7.py

@@ -49,7 +49,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, variant="s7-50", sys_clk_freq=int(100e6), with_spi_flash=False, with_led_chaser=True, **kwargs):
+    def __init__(self, variant="s7-50", sys_clk_freq=100e6, with_spi_flash=False, with_led_chaser=True, **kwargs):
         platform = digilent_arty_s7.Platform(variant=variant)
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/digilent_arty_z7.py

@@ -53,7 +53,7 @@ class _CRG(LiteXModule):
 
 
 class BaseSoC(SoCCore):
-    def __init__(self, variant="z7-20", toolchain="vivado", sys_clk_freq=int(125e6),
+    def __init__(self, variant="z7-20", toolchain="vivado", sys_clk_freq=125e6,
                  with_led_chaser=True, **kwargs):
         platform = digilent_arty_z7.Platform(variant=variant, toolchain=toolchain)
 

litex_boards/targets/digilent_atlys.py

@@ -149,8 +149,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, with_ethernet=True, with_etherbone=False, eth_phy=0, **kwargs):
-        sys_clk_freq = int(75e6)
+    def __init__(self, sys_clk_freq=75e6, with_ethernet=True, with_etherbone=False, eth_phy=0, **kwargs):
         platform = digilent_atlys.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/digilent_basys3.py

@@ -39,7 +39,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(75e6), with_led_chaser=True, with_video_terminal=False, **kwargs):
+    def __init__(self, sys_clk_freq=75e6, with_led_chaser=True, with_video_terminal=False, **kwargs):
         platform = digilent_basys3.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/digilent_cmod_a7.py

@@ -104,7 +104,7 @@ def addAsyncSram(soc, platform, name, origin, size):
 class BaseSoC(SoCCore):
     def __init__(self,  variant="a7-35",
         toolchain       = "vivado",
-        sys_clk_freq    = int(100e6),
+        sys_clk_freq    = 100e6,
         with_led_chaser = True,
         with_spi_flash  = False,
         **kwargs):

litex_boards/targets/digilent_genesys2.py

@@ -46,7 +46,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False,
+    def __init__(self, sys_clk_freq=100e6, with_ethernet=False, with_etherbone=False,
                  with_led_chaser=True, **kwargs):
         platform = digilent_genesys2.Platform()
 

litex_boards/targets/digilent_nexys4.py

@@ -166,7 +166,7 @@ def addCellularRAM(soc, platform, name, origin):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(75e6), with_led_chaser=True, with_ethernet=False, with_etherbone=False, with_video_terminal=False, with_video_framebuffer=False, **kwargs):
+    def __init__(self, sys_clk_freq=75e6, with_led_chaser=True, with_ethernet=False, with_etherbone=False, with_video_terminal=False, with_video_framebuffer=False, **kwargs):
         platform = digilent_nexys4.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/digilent_nexys4ddr.py

@@ -53,7 +53,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, with_etherbone=False,
+    def __init__(self, sys_clk_freq=75e6, with_ethernet=False, with_etherbone=False,
                  with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False,
                  **kwargs):
         platform = digilent_nexys4ddr.Platform()

litex_boards/targets/digilent_nexys_video.py

@@ -75,7 +75,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_ethernet=False,
+    def __init__(self, toolchain="vivado", sys_clk_freq=100e6, with_ethernet=False,
                  with_led_chaser=True, with_sata=False, sata_gen="gen2", with_sata_pll_refclk=False, vadj="1.2V", with_video_terminal=False,
                  with_video_framebuffer=False, **kwargs):
         platform = digilent_nexys_video.Platform(toolchain=toolchain)

litex_boards/targets/digilent_pynq_z1.py

@@ -58,7 +58,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_led_chaser=True,
+    def __init__(self, toolchain="vivado", sys_clk_freq=100e6, with_led_chaser=True,
                 with_video_terminal=False, with_video_framebuffer=False, **kwargs):
         platform = digilent_pynq_z1.Platform()
 

litex_boards/targets/digilent_zedboard.py

@@ -52,7 +52,7 @@ class _CRG(LiteXModule):
 class BaseSoC(SoCCore):
     mem_map = {"csr": 0x43c0_0000}  # default GP0 address on Zynq
 
-    def __init__(self, sys_clk_freq, with_led_chaser=True, **kwargs):
+    def __init__(self, sys_clk_freq=100e6, with_led_chaser=True, **kwargs):
         platform = digilent_zedboard.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/ebaz4205.py

@@ -43,7 +43,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, **kwargs):
+    def __init__(self, sys_clk_freq=100e6, with_led_chaser=True, **kwargs):
         platform = ebaz4205.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/efinix_t8f81_dev_kit.py

@@ -45,7 +45,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, bios_flash_offset, sys_clk_freq, with_led_chaser=True, **kwargs):
+    def __init__(self, bios_flash_offset, sys_clk_freq=33.333e6, with_led_chaser=True, **kwargs):
         platform = efinix_t8f81_dev_kit.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py

@@ -49,7 +49,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(200e6),
+    def __init__(self, sys_clk_freq=200e6,
         with_spi_flash = False,
         with_hyperram  = False,
         with_ethernet  = False,

litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py

@@ -44,7 +44,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(75e6),
+    def __init__(self, sys_clk_freq=75e6,
         with_spi_flash  = False,
         with_ethernet   = False,
         with_etherbone  = False,

litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py

@@ -42,7 +42,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), with_spi_flash=False, with_led_chaser=True, **kwargs):
+    def __init__(self, sys_clk_freq=100e6, with_spi_flash=False, with_led_chaser=True, **kwargs):
         platform = efinix_trion_t20_bga256_dev_kit.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py

@@ -40,7 +40,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), with_spi_flash=False, with_led_chaser=True, **kwargs):
+    def __init__(self, sys_clk_freq=100e6, with_spi_flash=False, with_led_chaser=True, **kwargs):
         platform = efinix_trion_t20_mipi_dev_kit.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/efinix_xyloni_dev_kit.py

@@ -44,7 +44,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, bios_flash_offset, sys_clk_freq, with_led_chaser=True, **kwargs):
+    def __init__(self, bios_flash_offset, sys_clk_freq=33.333e6,, with_led_chaser=True, **kwargs):
         platform = efinix_xyloni_dev_kit.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/ego1.py

@@ -36,7 +36,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, with_video_terminal=False, **kwargs):
+    def __init__(self, sys_clk_freq=100e6, with_led_chaser=True, with_video_terminal=False, **kwargs):
         platform = ego1.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/enclustra_mercury_kx2.py

@@ -45,7 +45,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, **kwargs):
+    def __init__(self, sys_clk_freq=125e6, with_led_chaser=True, **kwargs):
         platform = enclustra_mercury_kx2.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/enclustra_mercury_xu5.py

@@ -53,7 +53,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(125e6), with_led_chaser=True, **kwargs):
+    def __init__(self, sys_clk_freq=125e6, with_led_chaser=True, **kwargs):
         platform = enclustra_mercury_xu5.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/fairwaves_xtrx.py

@@ -63,7 +63,7 @@ class CRG(LiteXModule):
 # BaseSoC -----------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, with_led_chaser=True, **kwargs):
+    def __init__(self, sys_clk_freq=125e6, with_pcie=False, with_led_chaser=True, **kwargs):
         platform = fairwaves_xtrx.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/fpc_iii.py

@@ -76,7 +76,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(80e6), toolchain="trellis", with_ethernet=False,
+    def __init__(self, sys_clk_freq=80e6, toolchain="trellis", with_ethernet=False,
                  with_etherbone=False, with_led_chaser=True, **kwargs):
         platform = fpc_iii.Platform(toolchain=toolchain)
 

litex_boards/targets/fpgawars_alhambra2.py

@@ -46,7 +46,7 @@ class _CRG(LiteXModule):
 
 class BaseSoC(SoCCore):
 
-    def __init__(self, sys_clk_freq=int(12e6), with_led_chaser=True, bios_flash_offset=0x50000, **kwargs):
+    def __init__(self, sys_clk_freq=12e6, with_led_chaser=True, bios_flash_offset=0x50000, **kwargs):
 
         platform = fpgawars_alhambra2.Platform()
         kwargs["integrated_rom_size"] = 0

litex_boards/targets/gsd_butterstick.py

@@ -80,7 +80,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, revision="1.0", device="85F", sdram_device="MT41K64M16", sys_clk_freq=int(60e6), 
+    def __init__(self, revision="1.0", device="85F", sdram_device="MT41K64M16", sys_clk_freq=60e6,
         toolchain="trellis", with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", 
         eth_dynamic_ip   = False,
         with_spi_flash   = False,

litex_boards/targets/gsd_orangecrab.py

@@ -145,7 +145,7 @@ class _CRGSDRAM(LiteXModule):
 
 class BaseSoC(SoCCore):
     def __init__(self, revision="0.2", device="25F", sdram_device="MT41K64M16",
-                 sys_clk_freq=int(48e6), toolchain="trellis", with_led_chaser=True, **kwargs):
+                 sys_clk_freq=48e6, toolchain="trellis", with_led_chaser=True, **kwargs):
         platform = gsd_orangecrab.Platform(revision=revision, device=device ,toolchain=toolchain)
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/hackaday_hadbadge.py

@@ -53,7 +53,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, toolchain="trellis", sys_clk_freq=int(48e6), sdram_module_cls="AS4C32M8", **kwargs):
+    def __init__(self, toolchain="trellis", sys_clk_freq=48e6, sdram_module_cls="AS4C32M8", **kwargs):
         platform = hackaday_hadbadge.Platform(toolchain=toolchain)
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/hpcstore_xc7k420t.py

@@ -65,7 +65,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6),
+    def __init__(self, sys_clk_freq=100e6,
         io_voltage="3.3V",
         with_led_chaser = True,
         with_pcie       = False,

litex_boards/targets/icebreaker.py

@@ -67,7 +67,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, bios_flash_offset, sys_clk_freq=int(24e6), with_led_chaser=True,
+    def __init__(self, bios_flash_offset, sys_clk_freq=24e6, with_led_chaser=True,
                  with_video_terminal=False, **kwargs):
         platform = icebreaker.Platform()
         platform.add_extension(icebreaker.break_off_pmod)

litex_boards/targets/icebreaker_bitsy.py

@@ -98,7 +98,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, bios_flash_offset, sys_clk_freq=int(24e6), revision="v1", **kwargs):
+    def __init__(self, bios_flash_offset, sys_clk_freq=24e6, revision="v1", **kwargs):
         platform = icebreaker_bitsy.Platform(revision=revision)
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/isx_im1283.py

@@ -49,7 +49,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(80e6), with_led_chaser=True, **kwargs):
+    def __init__(self, sys_clk_freq=80e6, with_led_chaser=True, **kwargs):
         platform = isx_im1283.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------

litex_boards/targets/jungle_electronics_fireant.py

@@ -58,7 +58,7 @@ serial = [
 
 class BaseSoC(SoCCore):
     mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
-    def __init__(self, bios_flash_offset, sys_clk_freq, with_led_chaser=True, **kwargs):
+    def __init__(self, bios_flash_offset, sys_clk_freq=33.333e6, with_led_chaser=True, **kwargs):
         platform = jungle_electronics_fireant.Platform()
         platform.add_extension(serial)
 

litex_boards/targets/kosagi_fomu.py

@@ -69,7 +69,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, bios_flash_offset, spi_flash_module="AT25SF161", sys_clk_freq=int(12e6),
+    def __init__(self, bios_flash_offset, spi_flash_module="AT25SF161", sys_clk_freq=12e6,
                  with_led_chaser=True, **kwargs):
         platform = kosagi_fomu_pvt.Platform()
 

litex_boards/targets/kosagi_netv2.py

@@ -61,7 +61,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, variant="a7-35", sys_clk_freq=int(100e6), with_pcie=False,
+    def __init__(self, variant="a7-35", sys_clk_freq=100e6, with_pcie=False,
                  with_ethernet=False, with_led_chaser=True, **kwargs):
         platform = kosagi_netv2.Platform(variant=variant)
 

litex_boards/targets/krtkl_snickerdoodle.py

@@ -63,7 +63,7 @@ class _CRG(LiteXModule):
 
 class BaseSoC(SoCCore):
 
-    def __init__(self, variant="z7-10", sys_clk_freq=int(100e6), with_led_chaser=True,
+    def __init__(self, variant="z7-10", sys_clk_freq=100e6, with_led_chaser=True,
         ext_clk_freq = None,
         xci_file     = None,
         **kwargs):

litex_boards/targets/lambdaconcept_ecpix5.py

@@ -75,7 +75,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, device="85F", sys_clk_freq=int(75e6), toolchain="trellis",
+    def __init__(self, device="85F", sys_clk_freq=75e6, toolchain="trellis",
         with_ethernet          = False,
         with_etherbone         = False,
         with_video_terminal    = False,

litex_boards/targets/lattice_crosslink_nx_evn.py

@@ -64,7 +64,7 @@ class BaseSoC(SoCCore):
         "sram" : 0x40000000,
         "csr"  : 0xf0000000,
     }
-    def __init__(self, sys_clk_freq=int(75e6), device="LIFCL-40-9BG400C", toolchain="radiant", with_led_chaser=True, **kwargs):
+    def __init__(self, sys_clk_freq=75e6, device="LIFCL-40-9BG400C", toolchain="radiant", with_led_chaser=True, **kwargs):
         platform = lattice_crosslink_nx_evn.Platform(device=device, toolchain=toolchain)
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/lattice_crosslink_nx_vip.py

@@ -64,7 +64,7 @@ class BaseSoC(SoCCore):
         "sram": 0x40000000,
         "csr":  0xf0000000,
     }
-    def __init__(self, sys_clk_freq=int(75e6), hyperram="none", toolchain="radiant",
+    def __init__(self, sys_clk_freq=75e6, hyperram="none", toolchain="radiant",
                  with_led_chaser=True, **kwargs):
         platform = lattice_crosslink_nx_vip.Platform(toolchain=toolchain)
         platform.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}")

litex_boards/targets/lattice_ecp5_evn.py

@@ -44,7 +44,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(50e6), x5_clk_freq=None, toolchain="trellis",
+    def __init__(self, sys_clk_freq=50e6, x5_clk_freq=None, toolchain="trellis",
                  with_led_chaser=True, **kwargs):
         platform = lattice_ecp5_evn.Platform(toolchain=toolchain)
 

litex_boards/targets/lattice_ecp5_vip.py

@@ -83,7 +83,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(50e6), toolchain="trellis",
+    def __init__(self, sys_clk_freq=50e6, toolchain="trellis",
         with_led_chaser        = True,
         with_video_terminal    = True,
         with_video_framebuffer = False,

litex_boards/targets/lattice_ice40up5k_evn.py

@@ -57,7 +57,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, bios_flash_offset, sys_clk_freq=int(12e6), with_led_chaser=True, **kwargs):
+    def __init__(self, bios_flash_offset, sys_clk_freq=12e6, with_led_chaser=True, **kwargs):
         platform = lattice_ice40up5k_evn.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/lattice_versa_ecp5.py

@@ -74,7 +74,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(75e6), device="LFE5UM5G", with_ethernet=False,
+    def __init__(self, sys_clk_freq=75e6, device="LFE5UM5G", with_ethernet=False,
                  with_etherbone=False, with_led_chaser=True, eth_ip="192.168.1.50", eth_phy=0,
                  toolchain="trellis", **kwargs):
         platform = lattice_versa_ecp5.Platform(toolchain=toolchain, device=device)

litex_boards/targets/limesdr_mini_v2.py

@@ -68,7 +68,7 @@ class BoardInfo(LiteXModule, AutoCSR):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(80e6), toolchain="trellis",
+    def __init__(self, sys_clk_freq=80e6, toolchain="trellis",
         with_usb_fifo   = True, with_usb_fifo_loopback=False,
         with_led_chaser = True,
         **kwargs):

litex_boards/targets/linsn_rv901t.py

@@ -48,7 +48,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, with_etherbone=False, eth_phy=0, with_led_chaser=True, **kwargs):
+    def __init__(self, sys_clk_freq=75e6, with_ethernet=False, with_etherbone=False, eth_phy=0, with_led_chaser=True, **kwargs):
         platform     = linsn_rv901t.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/litex_acorn_baseboard.py

@@ -59,7 +59,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis",
+    def __init__(self, sys_clk_freq=75e6, toolchain="trellis",
         with_spi_flash      = False,
         with_ethernet       = False,
         with_etherbone      = False,

litex_boards/targets/logicbone.py

@@ -91,7 +91,7 @@ class _CRG(LiteXModule):
 
 class BaseSoC(SoCCore):
     def __init__(self, revision="rev0", device="45F", sdram_device="MT41K512M16",
-        sys_clk_freq    = int(75e6),
+        sys_clk_freq    = 75e6,
         with_ethernet   = False,
         with_led_chaser = True,
         toolchain       = "trellis",

litex_boards/targets/machdyne_krote.py

@@ -72,7 +72,7 @@ class _CRG(LiteXModule):
 
 class BaseSoC(SoCCore):
     mem_map = {**SoCCore.mem_map, **{"spiflash": 0x20000000}}
-    def __init__(self, bios_flash_offset, sys_clk_freq=int(100e6), with_led_chaser=True, **kwargs):
+    def __init__(self, bios_flash_offset, sys_clk_freq=100e6, with_led_chaser=True, **kwargs):
         platform = machdyne_krote.Platform()
 
         # Disable Integrated ROM since too large for iCE40.

litex_boards/targets/machdyne_schoko.py

@@ -106,7 +106,7 @@ class BaseSoC(SoCCore):
         "usb_ohci":     0xc0000000,
     }}
     def __init__(self, revision="v1", device="45F", sdram_rate="1:2",
-                 sys_clk_freq=int(40e6), toolchain="trellis", with_led_chaser=True, with_usb_host=False, **kwargs):
+                 sys_clk_freq=40e6, toolchain="trellis", with_led_chaser=True, with_usb_host=False, **kwargs):
         platform = machdyne_schoko.Platform(revision=revision, device=device ,toolchain=toolchain)
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/micronova_mercury2.py

@@ -109,7 +109,7 @@ class BaseSoC(SoCCore):
     def __init__(self, 
         variant         = "a7-35",
         toolchain       = "vivado",
-        sys_clk_freq    = int(100e6),
+        sys_clk_freq    = 100e6,
         with_led_chaser = True,
         **kwargs):
         platform = micronova_mercury2.Platform()

litex_boards/targets/mist.py

@@ -53,7 +53,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, with_video_terminal=False, **kwargs):
+    def __init__(self, sys_clk_freq=50e6, with_led_chaser=True, with_video_terminal=False, **kwargs):
         platform = mist.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/mnt_rkx7.py

@@ -75,7 +75,7 @@ class BaseSoC(SoCCore):
         "usb_ohci"         : 0xc0000000,
     }}
 
-    def __init__(self, sys_clk_freq=int(100e6), with_ethernet=True, with_etherbone=False,
+    def __init__(self, sys_clk_freq=100e6, with_ethernet=True, with_etherbone=False,
         with_spi_flash=True, with_usb_host=False, **kwargs):
         platform = mnt_rkx7.Platform()
 

litex_boards/targets/muselab_icesugar.py

@@ -56,7 +56,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, bios_flash_offset, sys_clk_freq=int(24e6), with_led_chaser=True,
+    def __init__(self, bios_flash_offset, sys_clk_freq=24e6, with_led_chaser=True,
                  with_video_terminal=False, **kwargs):
         platform = muselab_icesugar.Platform()
 

litex_boards/targets/myminieye_runber.py

@@ -35,7 +35,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(12e6), with_led_chaser=True, **kwargs):
+    def __init__(self, sys_clk_freq=12e6, with_led_chaser=True, **kwargs):
         platform = myminieye_runber.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/newae_cw305.py

@@ -58,7 +58,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, **kwargs):
+    def __init__(self, sys_clk_freq=100e6, with_led_chaser=True, **kwargs):
         platform = newae_cw305.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/numato_aller.py

@@ -56,7 +56,7 @@ class CRG(LiteXModule):
 # BaseSoC -----------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, with_pcie=False, **kwargs):
+    def __init__(self, sys_clk_freq=100e6, with_led_chaser=True, with_pcie=False, **kwargs):
         platform = numato_aller.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/numato_mimas_a7.py

@@ -49,7 +49,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, with_ethernet=False,
+    def __init__(self, sys_clk_freq=100e6, with_led_chaser=True, with_ethernet=False,
                  **kwargs):
         platform = numato_mimas_a7.Platform()
 

litex_boards/targets/numato_nereid.py

@@ -53,7 +53,7 @@ class CRG(LiteXModule):
 # BaseSoC -----------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, **kwargs):
+    def __init__(self, sys_clk_freq=100e6, with_pcie=False, **kwargs):
         platform = numato_nereid.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/numato_tagus.py

@@ -57,7 +57,7 @@ class CRG(LiteXModule):
 # BaseSoC -----------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, with_pcie=False, **kwargs):
+    def __init__(self, sys_clk_freq=100e6, with_led_chaser=True, with_pcie=False, **kwargs):
         platform = numato_tagus.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/pano_logic_g2.py

@@ -45,7 +45,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, revision, sys_clk_freq=int(50e6), with_ethernet=False, with_etherbone=False,
+    def __init__(self, revision, sys_clk_freq=50e6, with_ethernet=False, with_etherbone=False,
                  eth_ip="192.168.1.50", with_led_chaser=True, **kwargs):
         platform = pano_logic_g2.Platform(revision=revision)
         if with_etherbone:

litex_boards/targets/qmtech_10cl006.py

@@ -63,7 +63,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(50e6), with_daughterboard=False,
+    def __init__(self, sys_clk_freq=50e6, with_daughterboard=False,
                  with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
                  with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False,
                  sdram_rate="1:1", **kwargs):

litex_boards/targets/qmtech_5cefa2.py

@@ -76,7 +76,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(105e6), with_daughterboard=False,
+    def __init__(self, sys_clk_freq=105e6, with_daughterboard=False,
                  with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
                  with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False,
                  sdram_rate="1:1", **kwargs):

litex_boards/targets/qmtech_ep4ce15_starter_kit.py

@@ -60,7 +60,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(50e6), with_jtaguart=False, with_jtagbone=False,
+    def __init__(self, sys_clk_freq=50e6, with_jtaguart=False, with_jtagbone=False,
                  with_led_chaser=True, sdram_rate="1:1", **kwargs):
         platform = qmtech_ep4ce15_starter_kit.Platform()
 

litex_boards/targets/qmtech_ep4cex5.py

@@ -72,7 +72,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, variant="ep4ce15", sys_clk_freq=int(50e6), with_daughterboard=False,
+    def __init__(self, variant="ep4ce15", sys_clk_freq=50e6, with_daughterboard=False,
                  with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
                  with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False,
                  sdram_rate="1:1", **kwargs):

litex_boards/targets/qmtech_ep4cgx150.py

@@ -72,7 +72,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(50e6), with_daughterboard=False,
+    def __init__(self, sys_clk_freq=50e6, with_daughterboard=False,
                  with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
                  with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False,
                  sdram_rate="1:1", **kwargs):

litex_boards/targets/qmtech_wukong.py

@@ -72,7 +72,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), board_version=1, speed_grade=-2,
+    def __init__(self, sys_clk_freq=100e6, board_version=1, speed_grade=-2,
                  with_ethernet=False, with_etherbone=False,
                  eth_ip="192.168.1.50", with_led_chaser=True, with_video_terminal=False,
                  with_video_framebuffer=False, video_timing="640x480@60Hz", **kwargs):

litex_boards/targets/qmtech_xc7a35t.py

@@ -67,7 +67,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_daughterboard=False,
+    def __init__(self, toolchain="vivado", sys_clk_freq=100e6, with_daughterboard=False,
                  with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
                  with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False,
                  with_jtagbone=True, with_spi_flash=False, **kwargs):

litex_boards/targets/quicklogic_quickfeather.py

@@ -47,7 +47,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(10e6), with_led_chaser=True, with_gpio_in=True, **kwargs):
+    def __init__(self, sys_clk_freq=10e6, with_led_chaser=True, with_gpio_in=True, **kwargs):
         platform = quicklogic_quickfeather.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/qwertyembedded_beaglewire.py

@@ -65,7 +65,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, bios_flash_offset, sys_clk_freq=int(50e6), **kwargs):
+    def __init__(self, bios_flash_offset, sys_clk_freq=50e6, **kwargs):
         platform = qwertyembedded_beaglewire.Platform()
 
         # Disable Integrated ROM since too large for iCE40.

litex_boards/targets/radiona_ulx3s.py

@@ -87,7 +87,7 @@ class _CRG(LiteXModule):
 
 class BaseSoC(SoCCore):
     def __init__(self, device="LFE5U-45F", revision="2.0", toolchain="trellis",
-        sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", sdram_rate="1:1",
+        sys_clk_freq=50e6, sdram_module_cls="MT48LC16M16", sdram_rate="1:1",
         with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False,
         with_spi_flash=False, **kwargs):
         platform = radiona_ulx3s.Platform(device=device, revision=revision, toolchain=toolchain)

litex_boards/targets/rcs_arctic_tern_bmc_card.py

@@ -93,7 +93,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(50e6), toolchain="trellis",
+    def __init__(self, sys_clk_freq=50e6, toolchain="trellis",
         with_video_colorbars   = False,
         with_video_terminal    = True,
         with_video_framebuffer = False,

litex_boards/targets/redpitaya.py

@@ -48,7 +48,7 @@ class _CRG(LiteXModule):
 
 
 class BaseSoC(SoCCore):
-    def __init__(self, board, sys_clk_freq=int(100e6), with_led_chaser=True, **kwargs):
+    def __init__(self, board, sys_clk_freq=100e6, with_led_chaser=True, **kwargs):
         platform = redpitaya.Platform(board)
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/rz_easyfpga.py

@@ -57,7 +57,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, sdram_rate="1:1", **kwargs):
+    def __init__(self, sys_clk_freq=50e6, with_led_chaser=True, sdram_rate="1:1", **kwargs):
         platform = rz_easyfpga.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/scarabhardware_minispartan6.py

@@ -66,7 +66,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(80e6), sdram_rate="1:1", with_led_chaser=True,
+    def __init__(self, sys_clk_freq=80e6, sdram_rate="1:1", with_led_chaser=True,
                  with_video_terminal=False, with_video_framebuffer=False, **kwargs):
         platform = scarabhardware_minispartan6.Platform()
 

litex_boards/targets/seeedstudio_spartan_edge_accelerator.py

@@ -62,7 +62,7 @@ class _CRG(LiteXModule):
 
 class BaseSoC(SoCCore):
     
-    def __init__(self, sys_clk_freq=int(100e6),
+    def __init__(self, sys_clk_freq=100e6,
         with_led_chaser     = True,
         with_jtagbone       = False,
         with_video_terminal = True,

litex_boards/targets/siglent_sds1104xe.py

@@ -66,7 +66,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), with_etherbone=True, eth_ip="192.168.1.50", with_video_terminal=False, with_video_framebuffer=False, **kwargs):
+    def __init__(self, sys_clk_freq=100e6, with_etherbone=True, eth_ip="192.168.1.50", with_video_terminal=False, with_video_framebuffer=False, **kwargs):
         platform = siglent_sds1104xe.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/sipeed_tang_nano.py

@@ -62,7 +62,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCMini):
-    def __init__(self, sys_clk_freq=int(48e6), with_led_chaser=True, **kwargs):
+    def __init__(self, sys_clk_freq=48e6, with_led_chaser=True, **kwargs):
         platform = sipeed_tang_nano.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/sipeed_tang_nano_4k.py

@@ -62,7 +62,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(27e6), with_hyperram=False, with_led_chaser=True, with_video_terminal=True, **kwargs):
+    def __init__(self, sys_clk_freq=27e6, with_hyperram=False, with_led_chaser=True, with_video_terminal=True, **kwargs):
         platform = sipeed_tang_nano_4k.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/sipeed_tang_nano_9k.py

@@ -62,7 +62,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(27e6), bios_flash_offset=0x0,
+    def __init__(self, sys_clk_freq=27e6, bios_flash_offset=0x0,
                  with_led_chaser=True,  with_video_terminal=False, **kwargs):
         platform = sipeed_tang_nano_9k.Platform()
 

litex_boards/targets/sipeed_tang_primer.py

@@ -39,7 +39,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(24e6), with_led_chaser=True, **kwargs):
+    def __init__(self, sys_clk_freq=24e6, with_led_chaser=True, **kwargs):
         platform = sipeed_tang_primer.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/sipeed_tang_primer_20k.py

@@ -95,7 +95,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(48e6),
+    def __init__(self, sys_clk_freq=48e6,
         with_spi_flash      = False,
         with_led_chaser     = True,
         with_rgb_led        = False,

litex_boards/targets/sitlinv_a_e115fb.py

@@ -40,7 +40,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, **kwargs):
+    def __init__(self, sys_clk_freq=50e6, with_led_chaser=True, **kwargs):
         platform = sitlinv_a_e115fb.Platform()
 
         # CRG --------------------------------------------------------------------------------------

litex_boards/targets/sitlinv_stlv7325.py

@@ -60,7 +60,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6),
+    def __init__(self, sys_clk_freq=100e6,
         with_ethernet   = False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
         with_led_chaser = True,
         with_pcie       = False,