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- use 1e9/freq for default_clk_period
- add default serial on tinyfpga_bx
- use S6PLL on minispartan6
- add SPIFlash pins on versa_ecp5

litex_boards/community/platforms/ac701.py

@@ -198,7 +198,7 @@ _connectors = [
 
 class Platform(XilinxPlatform):
     default_clk_name = "clk156"
-    default_clk_period = 6.4
+    default_clk_period = 1e9/156.5e6
 
     def __init__(self):
         XilinxPlatform.__init__(self, "xc7a200t-fbg676-2", _io, _connectors, toolchain="vivado")

litex_boards/community/platforms/de10lite.py

@@ -96,7 +96,7 @@ _io = [
 
 class Platform(AlteraPlatform):
     default_clk_name = "clk50"
-    default_clk_period = 20
+    default_clk_period = 1e9/50e6
     create_rbf = False
 
     def __init__(self):

litex_boards/community/platforms/de1soc.py

@@ -33,7 +33,7 @@ _io = [
 
 class Platform(AlteraPlatform):
     default_clk_name = "clk50"
-    default_clk_period = 20
+    default_clk_period = 1e9/50e6
 
     def __init__(self):
         AlteraPlatform.__init__(self, "5CSEMA5F31C6", _io)

litex_boards/community/platforms/de2_115.py

@@ -33,7 +33,7 @@ _io = [
 
 class Platform(AlteraPlatform):
     default_clk_name = "clk50"
-    default_clk_period = 20
+    default_clk_period = 1e9/50e6
 
     def __init__(self):
         AlteraPlatform.__init__(self, "EP4CE115F29C7", _io)

litex_boards/community/platforms/sp605.py

@@ -155,7 +155,7 @@ _connectors = [
 
 class Platform(XilinxPlatform):
     default_clk_name = "clk200"
-    default_clk_period = 5.0
+    default_clk_period = 1e9/200e6
 
     def __init__(self):
         XilinxPlatform.__init__(self, "xc6slx45t-fgg484-3", _io, _connectors, toolchain="ise")

litex_boards/official/platforms/arty.py

@@ -237,7 +237,7 @@ _connectors = [
 
 class Platform(XilinxPlatform):
     default_clk_name = "clk100"
-    default_clk_period = 10.0
+    default_clk_period = 1e9/100e6
 
     def __init__(self, variant="a7-35"):
         device = {

litex_boards/official/platforms/avalanche.py

@@ -88,7 +88,7 @@ _io = [
 
 class Platform(MicrosemiPlatform):
     default_clk_name = "clk50"
-    default_clk_period = 20.0
+    default_clk_period = 1e9/50e6
 
     def __init__(self):
         MicrosemiPlatform.__init__(self, "MPF300TS_ES-FCG484-1", _io)

litex_boards/official/platforms/de0nano.py

@@ -96,7 +96,7 @@ _io = [
 
 class Platform(AlteraPlatform):
     default_clk_name = "clk50"
-    default_clk_period = 20
+    default_clk_period = 1e9/50e6
 
     def __init__(self):
         AlteraPlatform.__init__(self, "EP4CE22F17C6", _io)

litex_boards/official/platforms/genesys2.py

@@ -110,7 +110,7 @@ _connectors = [
 
 class Platform(XilinxPlatform):
     default_clk_name = "clk200"
-    default_clk_period = 5
+    default_clk_period = 1e9/200e6
 
     def __init__(self):
         XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado")

litex_boards/official/platforms/kc705.py

@@ -531,7 +531,7 @@ _connectors = [
 
 class Platform(XilinxPlatform):
     default_clk_name = "clk156"
-    default_clk_period = 6.4
+    default_clk_period = 1e9/156.5e6
 
     def __init__(self):
         XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado")

litex_boards/official/platforms/kcu105.py

@@ -486,7 +486,7 @@ _connectors = [
 
 class Platform(XilinxPlatform):
     default_clk_name = "clk125"
-    default_clk_period = 8.0
+    default_clk_period = 1e9/125e6
 
     def __init__(self):
         XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, _connectors, toolchain="vivado")

litex_boards/official/platforms/machxo3.py

@@ -35,7 +35,7 @@ _io = [
 
 class Platform(LatticePlatform):
     default_clk_name = "clk12"
-    default_clk_period = 83
+    default_clk_period = 1e9/12e6
 
     def __init__(self):
         LatticePlatform.__init__(self, "LCMXO3L-6900C-5BG256C", _io)

litex_boards/official/platforms/minispartan6.py

@@ -115,7 +115,7 @@ _connectors = [
 
 class Platform(XilinxPlatform):
     default_clk_name = "clk32"
-    default_clk_period = 31.25
+    default_clk_period = 1e9/32e6
 
     def __init__(self, device="xc6slx25"):
         XilinxPlatform.__init__(self, device+"-3-ftg256", _io, _connectors)

litex_boards/official/platforms/nexys4ddr.py

@@ -105,7 +105,7 @@ _io = [
 
 class Platform(XilinxPlatform):
     default_clk_name = "clk100"
-    default_clk_period = 10.0
+    default_clk_period = 1e9/100e6
 
     def __init__(self):
         XilinxPlatform.__init__(self, "xc7a100t-CSG324-1", _io, toolchain="vivado")

litex_boards/official/platforms/nexys_video.py

@@ -219,7 +219,7 @@ _connectors = [
 
 class Platform(XilinxPlatform):
     default_clk_name = "clk100"
-    default_clk_period = 10.0
+    default_clk_period = 1e9/100e6
 
     def __init__(self):
         XilinxPlatform.__init__(self, "xc7a200t-sbg484-1", _io, _connectors, toolchain="vivado")

litex_boards/official/platforms/versa_ecp3.py

@@ -79,7 +79,7 @@ _io = [
 
 class Platform(LatticePlatform):
     default_clk_name = "clk100"
-    default_clk_period = 10
+    default_clk_period = 1e9/100e6
 
     def __init__(self):
         LatticePlatform.__init__(self, "LFE3-35EA-6FN484C", _io)

litex_boards/official/platforms/versa_ecp5.py

@@ -35,6 +35,21 @@ _io = [
         Subsignal("tx", Pins("A11"), IOStandard("LVCMOS33")),
     ),
 
+    ("spiflash", 0, # clock needs to be accessed through USRMCLK
+        Subsignal("cs_n", Pins("R2")),
+        Subsignal("mosi", Pins("W2")),
+        Subsignal("miso", Pins("V2")),
+        Subsignal("wp", Pins("Y2")),
+        Subsignal("hold", Pins("W1")),
+        IOStandard("LVCMOS33"),
+    ),
+
+    ("spiflash4x", 0, # clock needs to be accessed through USRMCLK
+        Subsignal("cs_n", Pins("R2")),
+        Subsignal("dq", Pins("W2 V2 Y2 W1")),
+        IOStandard("LVCMOS33")
+    ),
+
     ("ddram", 0,
         Subsignal("a", Pins(
             "P2 C4 E5 F5 B3 F4 B5 E4",
@@ -181,7 +196,7 @@ _connectors = [
 
 class Platform(LatticePlatform):
     default_clk_name = "clk100"
-    default_clk_period = 10
+    default_clk_period = 1e9/100e6
 
     def __init__(self, **kwargs):
         LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381C", _io, _connectors, **kwargs)

litex_boards/official/targets/minispartan6.py

@@ -23,7 +23,7 @@ from litedram.phy import GENSDRPHY
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(Module):
-    def __init__(self, platform, clk_freq, use_s6pll=False):
+    def __init__(self, platform, clk_freq):
         self.clock_domains.cd_sys = ClockDomain()
         self.clock_domains.cd_sys_ps = ClockDomain()
 
@@ -32,52 +32,13 @@ class _CRG(Module):
         self.cd_sys.clk.attr.add("keep")
         self.cd_sys_ps.clk.attr.add("keep")
 
-        if use_s6pll:
         self.submodules.pll = pll = S6PLL(speedgrade=-1)
         pll.register_clkin(platform.request("clk32"), 32e6)
         pll.create_clkout(self.cd_sys, clk_freq)
         pll.create_clkout(self.cd_sys_ps, clk_freq, phase=270)
-        else:
-            f0 = 32*1000000
-            clk32 = platform.request("clk32")
-            clk32a = Signal()
-            self.specials += Instance("IBUFG", i_I=clk32, o_O=clk32a)
-            clk32b = Signal()
-            self.specials += Instance("BUFIO2", p_DIVIDE=1,
-                                      p_DIVIDE_BYPASS="TRUE", p_I_INVERT="FALSE",
-                                      i_I=clk32a, o_DIVCLK=clk32b)
-            f = Fraction(int(clk_freq), int(f0))
-            n, m, p = f.denominator, f.numerator, 8
-            assert f0/n*m == clk_freq
-            pll_lckd = Signal()
-            pll_fb = Signal()
-            pll = Signal(6)
-            self.specials.pll = Instance("PLL_ADV", p_SIM_DEVICE="SPARTAN6",
-                                         p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL",
-                                         p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT",
-                                         i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
-                                         p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
-                                         i_CLKIN1=clk32b, i_CLKIN2=0, i_CLKINSEL=1,
-                                         p_CLKIN1_PERIOD=1000000000/f0, p_CLKIN2_PERIOD=0.,
-                                         i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
-                                         o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
-                                         o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
-                                         o_CLKOUT2=pll[2], p_CLKOUT2_DUTY_CYCLE=.5,
-                                         o_CLKOUT3=pll[3], p_CLKOUT3_DUTY_CYCLE=.5,
-                                         o_CLKOUT4=pll[4], p_CLKOUT4_DUTY_CYCLE=.5,
-                                         o_CLKOUT5=pll[5], p_CLKOUT5_DUTY_CYCLE=.5,
-                                         p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//1,
-                                         p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//1,
-                                         p_CLKOUT2_PHASE=0., p_CLKOUT2_DIVIDE=p//1,
-                                         p_CLKOUT3_PHASE=0., p_CLKOUT3_DIVIDE=p//1,
-                                         p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1,  # sys
-                                         p_CLKOUT5_PHASE=270., p_CLKOUT5_DIVIDE=p//1,  # sys_ps
-            )
-            self.specials += Instance("BUFG", i_I=pll[4], o_O=self.cd_sys.clk)
-            self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys_ps.clk)
-            self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd)
 
-        self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
+        self.specials += Instance("ODDR2",
+            p_DDR_ALIGNMENT="NONE",
             p_INIT=0, p_SRTYPE="SYNC",
             i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
             i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk,

litex_boards/partner/platforms/fomu_evt.py

@@ -63,7 +63,7 @@ _connectors = [
 
 class Platform(LatticePlatform):
     default_clk_name = "clk48"
-    default_clk_period = 20.833
+    default_clk_period = 1e9/48e6
 
     gateware_size = 0x20000
 

litex_boards/partner/platforms/fomu_hacker.py

@@ -57,7 +57,7 @@ _connectors = [
 
 class Platform(LatticePlatform):
     default_clk_name = "clk48"
-    default_clk_period = 20.833
+    default_clk_period = 1e9/48e6
 
     gateware_size = 0x20000
 

litex_boards/partner/platforms/fomu_pvt.py

@@ -59,7 +59,7 @@ _connectors = [
 
 class Platform(LatticePlatform):
     default_clk_name = "clk48"
-    default_clk_period = 20.833
+    default_clk_period = 1e9/48e6
 
     gateware_size = 0x20000
 

litex_boards/partner/platforms/netv2.py

@@ -96,7 +96,7 @@ _io = [
 
 class Platform(XilinxPlatform):
     default_clk_name = "clk50"
-    default_clk_period = 20.0
+    default_clk_period = 1e9/50e6
 
     def __init__(self):
         XilinxPlatform.__init__(self, "xc7a35t-fgg484-2", _io, toolchain="vivado")

litex_boards/partner/platforms/tinyfpga_bx.py

@@ -59,10 +59,11 @@ serial = [
 
 class Platform(LatticePlatform):
     default_clk_name = "clk16"
-    default_clk_period = 62.5
+    default_clk_period = 1e9/16e6
 
     def __init__(self):
         LatticePlatform.__init__(self, "ice40-lp8k-cm81", _io, _connectors, toolchain="icestorm")
+        self.add_extension(serial)
 
     def create_programmer(self):
         return TinyProgProgrammer()

litex_boards/partner/platforms/ulx3s.py

@@ -69,7 +69,7 @@ _io = [
 
 class Platform(LatticePlatform):
     default_clk_name = "clk25"
-    default_clk_period = 40
+    default_clk_period = 1e9/25e6
 
     def __init__(self, device="LFE5U-45F", **kwargs):
         LatticePlatform.__init__(self, device + "-6BG381C", _io, **kwargs)