HDMI Terminal Support

Copyright notice update.

litex_boards/targets/digilent_pynq_z1.py

@@ -3,7 +3,7 @@
 #
 # This file is part of LiteX-Boards.
 #
-# Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>,
+# Copyright (c) 2022 Rakesh Peter <rakesh@stanproc.in>
 # SPDX-License-Identifier: BSD-2-Clause
 
 import os
@@ -17,21 +17,27 @@ from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
 from litex.soc.interconnect import axi
 from litex.soc.interconnect import wishbone
 
-from litex.soc.cores.clock import *
-
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *
+
+from litex.soc.cores.clock import *
+from litex.soc.cores.video import VideoS7HDMIPHY
 from litex.soc.cores.led import LedChaser
 
 # CRG ----------------------------------------------------------------------------------------------
-
 class _CRG(Module):
-    def __init__(self, platform, sys_clk_freq, use_ps7_clk=False):
+    def __init__(self, platform, sys_clk_freq, toolchain, use_ps7_clk=False, with_video_pll=False):
         self.rst = Signal()
         self.clock_domains.cd_sys = ClockDomain()
+        self.clock_domains.cd_hdmi = ClockDomain()
+        self.clock_domains.cd_hdmi5x = ClockDomain()
 
         # # #
 
+	# Clk
+        clk125 = platform.request("sysclk")
+
+	# PLL
         if use_ps7_clk:
             assert sys_clk_freq == 125e6
             self.comb += ClockSignal("sys").eq(ClockSignal("ps7"))
@@ -39,14 +45,23 @@ class _CRG(Module):
         else:
             self.submodules.pll = pll = S7PLL(speedgrade=-1)
             self.comb += pll.reset.eq(self.rst)
-            pll.register_clkin(platform.request("sysclk"), 125e6)
+            pll.register_clkin(clk125, 125e6)
             pll.create_clkout(self.cd_sys, sys_clk_freq)
             platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
+	# Video PLL.
+        if with_video_pll:
+            self.submodules.video_pll = video_pll = S7MMCM(speedgrade=-1)
+            video_pll.reset.eq(self.rst)
+            video_pll.register_clkin(clk125, 125e6)
+            video_pll.create_clkout(self.cd_hdmi,   40e6)
+            video_pll.create_clkout(self.cd_hdmi5x, 5*40e6)
+
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, **kwargs):
+    def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_led_chaser=True,
+                with_video_terminal=False, with_video_framebuffer=False, **kwargs):
         platform = pynq_z1.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -62,7 +77,7 @@ class BaseSoC(SoCCore):
             os.makedirs("xci", exist_ok=True)
             os.system("mv zybo_z7_ps7.txt xci/zybo_z7_ps7.xci")
             self.cpu.set_ps7_xci("xci/zybo_z7_ps7.xci")
-            
+
             # Connect AXI GP0 to the SoC with base address of 0x43c00000 (default one)
             wb_gp0  = wishbone.Interface()
             self.submodules += axi.AXI2Wishbone(
@@ -72,8 +87,13 @@ class BaseSoC(SoCCore):
             self.add_wb_master(wb_gp0)
 
         # CRG --------------------------------------------------------------------------------------
-        self.submodules.crg = _CRG(platform, sys_clk_freq)
-	
+        self.submodules.crg = _CRG(platform, sys_clk_freq, toolchain, with_video_pll=with_video_terminal)
+
+	# Video ------------------------------------------------------------------------------------
+        if with_video_terminal:
+            self.submodules.videophy = VideoS7HDMIPHY(platform.request("hdmi_tx"), clock_domain="hdmi")
+            self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
+
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:
             self.submodules.leds = LedChaser(
@@ -84,9 +104,11 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on PYNQ Z1")
-    parser.add_argument("--build",        action="store_true", help="Build bitstream")
-    parser.add_argument("--load",         action="store_true", help="Load bitstream")
-    parser.add_argument("--sys-clk-freq", default=125e6,       help="System clock frequency (default: 100MHz)")
+    parser.add_argument("--build",                  action="store_true", help="Build bitstream")
+    parser.add_argument("--load",                   action="store_true", help="Load bitstream")
+    parser.add_argument("--sys-clk-freq",           default=125e6,       help="System clock frequency (default: 125MHz)")
+    parser.add_argument("--with-video-terminal",    action="store_true", help="Enable Video Terminal (HDMI)")
+
     builder_args(parser)
     soc_core_args(parser)
     vivado_build_args(parser)
@@ -94,7 +116,8 @@ def main():
 
     soc = BaseSoC(
         sys_clk_freq = int(float(args.sys_clk_freq)),
-        **soc_core_argdict(args)
+	    with_video_terminal = args.with_video_terminal,
+	    **soc_core_argdict(args)
     )
     builder = Builder(soc, **builder_argdict(args))
     builder.build(**vivado_build_argdict(args), run=args.build)