digilent_arty: Allow exposing raw PMOD IOs (for tests with MicroPython).
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@ -250,6 +250,9 @@ _connectors = [
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# PMODS --------------------------------------------------------------------------------------------
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# PMODS --------------------------------------------------------------------------------------------
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def raw_pmod_io(pmod):
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return [(pmod, 0, Pins(" ".join([f"{pmod}:{i:d}" for i in range(8)])), IOStandard("LVCMOS33"))]
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def usb_pmod_io(pmod):
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def usb_pmod_io(pmod):
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return [
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return [
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# USB-UART PMOD: https://store.digilentinc.com/pmod-usbuart-usb-to-uart-interface/
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# USB-UART PMOD: https://store.digilentinc.com/pmod-usbuart-usb-to-uart-interface/
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@ -20,6 +20,7 @@ from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.gpio import GPIOTristate
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from litedram.modules import MT41K128M16
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from litedram.modules import MT41K128M16
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from litedram.phy import s7ddrphy
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from litedram.phy import s7ddrphy
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@ -64,7 +65,7 @@ class BaseSoC(SoCCore):
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def __init__(self, variant="a7-35", toolchain="vivado", sys_clk_freq=int(100e6),
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def __init__(self, variant="a7-35", toolchain="vivado", sys_clk_freq=int(100e6),
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with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50",
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with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50",
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eth_dynamic_ip=False, ident_version=True, with_led_chaser=True, with_jtagbone=True,
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eth_dynamic_ip=False, ident_version=True, with_led_chaser=True, with_jtagbone=True,
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with_mapped_flash=False, **kwargs):
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with_mapped_flash=False, with_pmod_gpio=False, **kwargs):
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platform = arty.Platform(variant=variant, toolchain=toolchain)
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platform = arty.Platform(variant=variant, toolchain=toolchain)
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# SoCCore ----------------------------------------------------------------------------------
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# SoCCore ----------------------------------------------------------------------------------
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@ -115,6 +116,11 @@ class BaseSoC(SoCCore):
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pads = platform.request_all("user_led"),
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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sys_clk_freq = sys_clk_freq)
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# GPIOs ------------------------------------------------------------------------------------
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if with_pmod_gpio:
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platform.add_extension(arty.raw_pmod_io("pmoda"))
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self.submodules.gpio = GPIOTristate(platform.request("pmoda"))
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# Build --------------------------------------------------------------------------------------------
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# Build --------------------------------------------------------------------------------------------
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def main():
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def main():
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@ -136,6 +142,7 @@ def main():
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parser.add_argument("--no-ident-version", action="store_false", help="Disable build time output")
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parser.add_argument("--no-ident-version", action="store_false", help="Disable build time output")
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parser.add_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support")
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parser.add_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support")
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parser.add_argument("--with-mapped-flash", action="store_true", help="Enable Memory Mapped Flash")
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parser.add_argument("--with-mapped-flash", action="store_true", help="Enable Memory Mapped Flash")
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parser.add_argument("--with-pmod-gpio", action="store_true", help="Enable GPIOs through PMOD") # FIXME: Temporary test.
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builder_args(parser)
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builder_args(parser)
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soc_core_args(parser)
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soc_core_args(parser)
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vivado_build_args(parser)
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vivado_build_args(parser)
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@ -154,6 +161,7 @@ def main():
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ident_version = args.no_ident_version,
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ident_version = args.no_ident_version,
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with_jtagbone = args.with_jtagbone,
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with_jtagbone = args.with_jtagbone,
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with_mapped_flash = args.with_mapped_flash,
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with_mapped_flash = args.with_mapped_flash,
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with_pmod_gpio = args.with_pmod_gpio,
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**soc_core_argdict(args)
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**soc_core_argdict(args)
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)
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)
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if args.sdcard_adapter == "numato":
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if args.sdcard_adapter == "numato":
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