rhsresearchllc_litefury: Remove since already supported by ./acorn.py --variant=cle-101.
This commit is contained in:
Florent Kermarrec
parent
4329a69128
commit
a48def1352
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 <linux.robotdude@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk200", 0,
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Subsignal("p", Pins("J19"), IOStandard("LVDS_25")),
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Subsignal("n", Pins("H19"), IOStandard("LVDS_25"))
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),
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# Leds
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("user_led", 0, Pins("G3"), IOStandard("LVCMOS33"), Misc("PULLUP"), Misc("DRIVE=8")),
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("user_led", 1, Pins("H3"), IOStandard("LVCMOS33"), Misc("PULLUP"), Misc("DRIVE=8")),
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("user_led", 2, Pins("G4"), IOStandard("LVCMOS33"), Misc("PULLUP"), Misc("DRIVE=8")),
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("user_led", 3, Pins("H4"), IOStandard("LVCMOS33"), Misc("PULLUP"), Misc("DRIVE=8")),
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# M.2 Led signal
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("m2_led", 0, Pins("M1"), IOStandard("LVCMOS33"), Misc("DRIVE=8")),
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# SMBus (M.2 spec has pullups on host)
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("smbus", 0,
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Subsignal("clk", Pins("Y11"), IOStandard("LVCMOS33")),
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Subsignal("data", Pins("Y12"), IOStandard("LVCMOS33")),
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Subsignal("alert_n", Pins("Y13"), IOStandard("LVCMOS33"))
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),
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# SPIFlash
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("flash", 0,
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Subsignal("cs_n", Pins("T19")),
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Subsignal("mosi", Pins("P22")),
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Subsignal("miso", Pins("R22")),
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Subsignal("hold", Pins("R21")),
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IOStandard("LVCMOS33")
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),
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("flash4x", 0, # clock needs to be accessed through STARTUPE2 (pad L12) (90 MHz EMC clock is available)
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Subsignal("cs_n", Pins("T19")),
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Subsignal("dq", Pins("P22", "R22", "P21", "R21")),
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IOStandard("LVCMOS33")
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),
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# PCIe clock request
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("pcie_clkreq_l", 0, Pins("G1"), IOStandard("LVCMOS33")),
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# PCIe
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("pcie_x1", 0,
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Subsignal("rst_n", Pins("J1"), IOStandard("LVCMOS33")),
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Subsignal("clk_p", Pins("F6")),
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Subsignal("clk_n", Pins("E6")),
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Subsignal("rx_p", Pins("B10")),
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Subsignal("rx_n", Pins("A10")),
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Subsignal("tx_p", Pins("B6")),
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Subsignal("tx_n", Pins("A6"))
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),
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("pcie_x4", 0,
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Subsignal("rst_n", Pins("J1"), IOStandard("LVCMOS33")),
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Subsignal("clk_p", Pins("F6")),
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Subsignal("clk_n", Pins("E6")),
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Subsignal("rx_p", Pins("B10 B8 D11 D9")),
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Subsignal("rx_n", Pins("A10 A8 C11 C9")),
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Subsignal("tx_p", Pins("B6 B4 D5 D7")),
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Subsignal("tx_n", Pins("A6 A4 C5 C7"))
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),
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# DDR3 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"M15 L21 M16 L18 K21 M18 M21 N20",
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"M20 N19 J21 M22 K22 N18 N22"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("L19 J20 L20"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("H20"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("K18"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("L16"), IOStandard("SSTL15")),
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Subsignal("dm", Pins("A19 G22"), IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"D19 B20 E19 A20 F19 C19 F20 C18",
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"E22 G21 D20 E21 C22 D21 B22 D22"),
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IOStandard("SSTL15"),
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Misc("IN_TERM=UNTUNED_SPLIT_50")),
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Subsignal("dqs_p", Pins("F18 B21"), IOStandard("DIFF_SSTL15")),
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Subsignal("dqs_n", Pins("E18 A21"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_p", Pins("K17"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("J17"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("H22"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("K19"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("K16"), IOStandard("LVCMOS15")),
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Misc("SLEW=FAST"),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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# Digital IO Header
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("IO", {
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# LVDS pins
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"dio1_p" : "W9",
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"dio1_n" : "Y9",
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"dio2_p" : "Y8",
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"dio2_n" : "Y7",
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"dio3_p" : "AA8",
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"dio3_n" : "AB8",
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"dio4_p" : "V9",
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"dio4_n" : "V8",
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# 3.3V DIO pins (or XADC)
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"aio1_p" : "J5",
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"aio1_n" : "H5",
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"aio2_p" : "K2",
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"aio2_n" : "J2",
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}
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),
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# Analog Header
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("XADC", {
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"aio1_p" : "J5",
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"aio1_n" : "H5",
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"aio2_p" : "K2",
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"aio2_n" : "J2",
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}
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk200"
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default_clk_period = 1e9/200e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7a100t-fgg484-2l", _io, _connectors, toolchain="vivado")
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# Enable fast startup so FPGA is up before PCIe root-complex initialization on host
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self.add_platform_command("set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN Div-1 [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]")
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self.add_platform_command("set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]")
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self.add_platform_command("set_property CFGBVS VCCO [current_design]")
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self.add_platform_command("set_property CONFIG_MODE SPIx4 [current_design]")
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self.add_platform_command("set_property CONFIG_VOLTAGE 3.3 [current_design]")
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format mcs -interface spix4 -size 16 "
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"-loadbit \"up 0x680000 {build_name}.bit\" -file {build_name}.mcs"]
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6)
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@ -1,124 +0,0 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2018-2019 Rohit Singh <rohit@rohitksingh.in>
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# Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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import sys
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from migen import *
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from litex_boards.platforms import litefury
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from litex.soc.interconnect.csr import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.clock import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import AS4C256M16D3A
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from litedram.phy import s7ddrphy
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from litepcie.phy.s7pciephy import S7PCIEPHY
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from litepcie.software import generate_litepcie_software
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# CRG ----------------------------------------------------------------------------------------------
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class CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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# Clk/Rst
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clk200 = platform.request("clk200")
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# PLL
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self.submodules.pll = pll = S7PLL()
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk200, 200e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC -----------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, **kwargs):
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platform = litefury.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on LiteFury",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(platform, sys_clk_freq)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq,
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iodelay_clk_freq = 200e6)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = AS4C256M16D3A(sys_clk_freq, "1:4"),
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origin = self.mem_map["main_ram"],
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size = kwargs.get("max_sdram_size", 0x20000000),
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l2_cache_size = kwargs.get("l2_size", 8192),
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l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
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l2_cache_reverse = True
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)
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
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data_width = 128,
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bar0_size = 0x20000)
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self.add_pcie(phy=self.pcie_phy, ndmas=1)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Aller")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
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parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
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parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_pcie = args.with_pcie,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.driver:
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generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
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if __name__ == "__main__":
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main()
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Reference in New Issue