target/efinix_ti60_f225: Add L2 Cache (16KB for now) to improve perfs/Coremark.
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@ -17,6 +17,7 @@ from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.hyperbus import HyperRAM
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@ -72,8 +73,28 @@ class BaseSoC(SoCCore):
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# HyperRAM ---------------------------------------------------------------------------------
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if with_hyperram:
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self.hyperram = HyperRAM(platform.request("hyperram"), latency=7, sys_clk_freq=sys_clk_freq)
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self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=32*1024*1024))
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# HyperRAM Parameters.
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hyperram_device = "W958D6NW"
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hyperram_size = 32*1024*1024
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hyperram_cache_size = 16*1024
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# HyperRAM Bus/Slave Interface.
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hyperram_bus = wishbone.Interface(data_width=32, address_width=32, addressing="word")
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self.bus.add_slave(name="main_ram", slave=hyperram_bus, region=SoCRegion(origin=0x40000000, size=hyperram_size))
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# HyperRAM L2 Cache.
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hyperram_cache = wishbone.Cache(
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cachesize = hyperram_cache_size//4,
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master = hyperram_bus,
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slave = wishbone.Interface(data_width=32, address_width=32, addressing="word")
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)
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hyperram_cache = FullMemoryWE()(hyperram_cache)
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self.hyperram_cache = hyperram_cache
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self.add_config("L2_SIZE", hyperram_cache_size)
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# HyperRAM Core.
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self.hyperram = HyperRAM(platform.request("hyperram"), latency=7, latency_mode="variable", sys_clk_freq=sys_clk_freq)
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self.comb += self.hyperram_cache.slave.connect(self.hyperram.bus)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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