Add target for LPDDR4 Test Board
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Jędrzej Boczar
parent
d5ce1901d8
commit
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("clk100", 0, Pins("L19"), IOStandard("LVCMOS33")),
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("user_led", 0, Pins("F8"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("C8"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("A8"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("D9"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("F9"), IOStandard("LVCMOS33")),
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("user_btn", 0, Pins("E8"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("B9"), IOStandard("LVCMOS33")),
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("user_btn", 2, Pins("C9"), IOStandard("LVCMOS33")),
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("user_btn", 3, Pins("E9"), IOStandard("LVCMOS33")),
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("serial", 0,
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Subsignal("tx", Pins("AB18")),
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Subsignal("rx", Pins("AA18")),
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IOStandard("LVCMOS33")
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),
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("serial", 1,
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Subsignal("tx", Pins("AA20")),
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Subsignal("rx", Pins("AB20")),
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IOStandard("LVCMOS33")
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),
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# LPDDR4 (not 1.2V, uses 1.1V or 0.6V depending on J10 jumper)
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("lpddr4", 0,
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Subsignal("clk_p", Pins("Y3"), IOStandard("DIFF_SSTL12")),
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Subsignal("clk_n", Pins("Y2"), IOStandard("DIFF_SSTL12")),
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Subsignal("cke", Pins("N4"), IOStandard("SSTL12")),
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Subsignal("odt", Pins("N5"), IOStandard("SSTL12")),
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Subsignal("reset_n", Pins("P4"), IOStandard("SSTL12")),
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Subsignal("cs", Pins("N3"), IOStandard("SSTL12")),
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Subsignal("ca", Pins("L3 L5 AA4 AA3 AB3 AB2"), IOStandard("SSTL12")),
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Subsignal("dq", Pins(
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"L1 K2 K1 K3 R1 P2 P1 N2",
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"W2 Y1 AA1 AB1 R2 T1 T3 U1"),
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IOStandard("SSTL12_T_DCI")),
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Subsignal("dqs_p", Pins("M2 U2"), IOStandard("DIFF_SSTL12")),
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Subsignal("dqs_n", Pins("M1 V2"), IOStandard("DIFF_SSTL12")),
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Subsignal("dmi", Pins("M3 W1"), IOStandard("SSTL12_T_DCI")),
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Misc("SLEW=FAST"),
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),
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# RGMII Ethernet
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("eth_ref_clk", 0, Pins("C12"), IOStandard("LVCMOS33")),
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("eth_clocks", 0,
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Subsignal("tx", Pins("E17")),
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Subsignal("rx", Pins("C17")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("E16"), IOStandard("LVCMOS33")),
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Subsignal("mdio", Pins("C14"), IOStandard("LVCMOS33")),
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Subsignal("mdc", Pins("B17"), IOStandard("LVCMOS33")),
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Subsignal("rx_ctl", Pins("A16"), IOStandard("LVCMOS33")),
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Subsignal("rx_data", Pins("B16 A15 B15 A14"), IOStandard("LVCMOS33")),
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Subsignal("tx_ctl", Pins("A13"), IOStandard("LVCMOS33")),
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Subsignal("tx_data", Pins("B21 B20 A19 A18"), IOStandard("LVCMOS33")),
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),
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# HyperRAM
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("hyperram", 0,
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Subsignal("clk", Pins("AB15")), # clk_n AB16
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Subsignal("rst_n", Pins("V17")),
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Subsignal("dq", Pins("W15 AA15 AA14 W14 Y14 V15 Y16 W17")),
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Subsignal("cs_n", Pins("AA16")),
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Subsignal("rwds", Pins("Y17")),
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IOStandard("LVCMOS33")
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),
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# SD Card
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("sdcard", 0,
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Subsignal("data", Pins("D20 D19 C22 D21"), Misc("PULLUP True")),
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Subsignal("cmd", Pins("C20"), Misc("PULLUP True")),
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Subsignal("clk", Pins("D22")),
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Subsignal("cd", Pins("B22")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self, device="xc7k70tfbg484-1"):
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XilinxPlatform.__init__(self, device, _io, toolchain="vivado")
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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def create_programmer(self):
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return OpenOCD("openocd_xc7_ft4232.cfg", "bscan_spi_xc7k70t.bit")
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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@ -0,0 +1,14 @@
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interface ftdi
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ftdi_vid_pid 0x0403 0x6011
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ftdi_channel 0
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ftdi_layout_init 0x00e8 0x60eb
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reset_config none
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source [find cpld/xilinx-xc7.cfg]
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source [find cpld/jtagspi.cfg]
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adapter_khz 25000
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proc fpga_program {} {
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global _CHIPNAME
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xc7_program $_CHIPNAME.tap
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}
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@ -0,0 +1,167 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from litex_boards.platforms import lpddr4_test_board
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT53E256M16D1
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from litedram.phy import lpddr4
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from liteeth.phy import LiteEthS7PHYRGMII
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from litehyperbus.core.hyperbus import HyperRAM
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, iodelay_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys8x = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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# # #
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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pll.register_clkin(platform.request("clk100"), 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq)
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pll.create_clkout(self.cd_sys8x, 8 * sys_clk_freq)
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pll.create_clkout(self.cd_idelay, iodelay_clk_freq)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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mem_map = {
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"hyperram": 0x20000000,
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}
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mem_map.update(SoCCore.mem_map)
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def __init__(self, *, sys_clk_freq=int(50e6), iodelay_clk_freq=200e6,
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with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
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with_hyperram=False, with_sdcard=False, with_jtagbone=True, with_uartbone=False,
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ident_version=True, **kwargs):
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platform = lpddr4_test_board.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on LPDDR4 Test Board",
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ident_version = ident_version,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, iodelay_clk_freq=iodelay_clk_freq)
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# LDDR4 SDRAM ------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = lpddr4.K7LPDDR4PHY(platform.request("lpddr4"),
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iodelay_clk_freq = iodelay_clk_freq,
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sys_clk_freq = sys_clk_freq,
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)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT53E256M16D1(sys_clk_freq, "1:8"),
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l2_cache_size = kwargs.get("l2_size", 8192),
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l2_cache_min_data_width = 256,
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)
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# HyperRAM ---------------------------------------------------------------------------------
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if with_hyperram:
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self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
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self.register_mem("hyperram", self.mem_map["hyperram"], self.hyperram.bus, 8*1024*1024)
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# SD Card ----------------------------------------------------------------------------------
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if with_sdcard:
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self.add_sdcard()
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.submodules.ethphy = LiteEthS7PHYRGMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
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# Jtagbone ---------------------------------------------------------------------------------
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if with_jtagbone:
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self.add_jtagbone()
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# UartBone ---------------------------------------------------------------------------------
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if with_uartbone:
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self.add_uartbone("serial", baudrate=1e6)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on LPDDR4 Test Board")
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target = parser.add_argument_group(title="Target options")
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target.add_argument("--build", action="store_true", help="Build bitstream")
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target.add_argument("--load", action="store_true", help="Load bitstream")
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target.add_argument("--flash", action="store_true", help="Flash bitstream")
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target.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency")
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target.add_argument("--iodelay-clk-freq", default=200e6, help="IODELAYCTRL frequency")
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ethopts = target.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Add Ethernet")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Add EtherBone")
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target.add_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address")
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target.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting")
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target.add_argument("--with-hyperram", action="store_true", help="Add HyperRAM")
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target.add_argument("--with-sdcard", action="store_true", help="Add SDCard")
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target.add_argument("--with-jtagbone", action="store_true", help="Add JTAGBone")
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target.add_argument("--with-uartbone", action="store_true", help="Add UartBone on 2nd serial")
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parser.add_argument("--no-ident-version", action="store_false", help="Disable build time output")
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builder_args(parser)
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soc_core_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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assert not (args.with_etherbone and args.eth_dynamic_ip)
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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iodelay_clk_freq = int(float(args.iodelay_clk_freq)),
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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eth_dynamic_ip = args.eth_dynamic_ip,
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with_hyperram = args.with_hyperram,
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with_sdcard = args.with_sdcard,
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with_jtagbone = args.with_jtagbone,
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with_uartbone = args.with_uartbone,
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ident_version = args.no_ident_version,
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**soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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vns = builder.build(**vivado_build_argdict(args), run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.flash(0, os.path.join(builder.gateware_dir, soc.build_name + ".bin"))
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if __name__ == "__main__":
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main()
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@ -126,6 +126,9 @@ class TestTargets(unittest.TestCase):
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# Microsemi PolarFire
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platforms.append("avalanche")
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# LPDDR4 Test Board
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platforms.append("lpddr4_test_board")
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for name in platforms:
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with self.subTest(platform=name):
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cmd = """\
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