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targets/lattice_certuspro_nx_vvml,lattice_certuspro_nx_evn: switch sys_clk to NXPLL

This commit is contained in:
Gwenhael Goavec-Merou 2024-07-03 12:36:28 +02:00
parent 9898672744
commit ac427feb0a
2 changed files with 28 additions and 18 deletions
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23
litex_boards/targets/lattice_certuspro_nx_evn.py
View File

@ -35,23 +35,28 @@ class _CRG(LiteXModule):
# # #
# Clk / Rst
self.rst_n = platform.request("user_btn", 0)
self.clk125 = platform.request("clk125")
self.rst_n = platform.request("user_btn", 0)
# Clocking
self.sys_clk = sys_osc = NXOSCA()
sys_osc.create_hf_clk(self.cd_sys, sys_clk_freq)
platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq)
self.hf_clk = NXOSCA()
hf_clk_freq = 25e6
self.hf_clk.create_hf_clk(self.cd_por, hf_clk_freq)
# Power on reset
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += por_done.eq(por_count == 0)
self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
self.specials += [
AsyncResetSynchronizer(self.cd_por, ~self.rst_n),
AsyncResetSynchronizer(self.cd_sys, ~por_done | self.rst)
]
self.specials += AsyncResetSynchronizer(self.cd_por, ~self.rst_n)
# PLL
self.sys_pll = sys_pll = NXPLL(platform=platform, create_output_port_clocks=True)
self.comb += sys_pll.reset.eq(self.rst | ~por_done)
sys_pll.register_clkin(self.clk125, 125e6)
sys_pll.create_clkout(self.cd_sys, sys_clk_freq)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~self.sys_pll.locked)
# BaseSoC ------------------------------------------------------------------------------------------

23
litex_boards/targets/lattice_certuspro_nx_vvml.py
View File

@ -35,23 +35,28 @@ class _CRG(LiteXModule):
# # #
# Clk / Rst
self.clk24 = platform.request("clk24")
self.rst_n = platform.request("gsrn")
# Clocking
self.sys_clk = sys_osc = NXOSCA()
sys_osc.create_hf_clk(self.cd_sys, sys_clk_freq)
platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq)
# Built in OSC
self.hf_clk = NXOSCA()
hf_clk_freq = 25e6
self.hf_clk.create_hf_clk(self.cd_por, hf_clk_freq)
# Power on reset
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += por_done.eq(por_count == 0)
self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
self.specials += [
AsyncResetSynchronizer(self.cd_por, ~self.rst_n),
AsyncResetSynchronizer(self.cd_sys, ~por_done | self.rst)
]
self.specials += AsyncResetSynchronizer(self.cd_por, ~self.rst_n)
# PLL
self.sys_pll = sys_pll = NXPLL(platform=platform, create_output_port_clocks=True)
self.comb += sys_pll.reset.eq(self.rst | ~por_done)
sys_pll.register_clkin(self.clk24, 24e6)
sys_pll.create_clkout(self.cd_sys, sys_clk_freq)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~self.sys_pll.locked)
# BaseSoC ------------------------------------------------------------------------------------------