Merge pull request #82 from Disasm/colorlight-5a-75e
Add Colorlight 5A-75E V7.1 board
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enjoy-digital
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# This file is Copyright (c) 2020 Vadim Kaushan <admin@disasm.info>
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# License: BSD
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# The Colorlight 5A-75E PCB and IOs have been documented by @derekmulcahy:
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# https://github.com/q3k/chubby75/issues/59
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice.programmer import OpenOCDJTAGProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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# Documented by @derekmulcahy
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_io_v7_1 = [
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# clock
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("clk25", 0, Pins("P6"), IOStandard("LVCMOS33")),
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# led
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("user_led_n", 0, Pins("P11"), IOStandard("LVCMOS33")),
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# btn
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("user_btn_n", 0, Pins("M13"), IOStandard("LVCMOS33")),
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# serial
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("serial", 0,
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Subsignal("tx", Pins("P11")), # led (J19 DATA_LED-)
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Subsignal("rx", Pins("M13")), # btn (J19 KEY+)
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IOStandard("LVCMOS33")
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),
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# spiflash (W25Q32JV)
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("spiflash", 0,
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# clk
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Subsignal("cs_n", Pins("N8")),
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#Subsignal("clk", Pins("")), driven through USRMCLK
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Subsignal("mosi", Pins("T8")),
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Subsignal("miso", Pins("T7")),
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IOStandard("LVCMOS33"),
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),
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# sdram (M12616161A)
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("sdram_clock", 0, Pins("C6"), IOStandard("LVCMOS33")),
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("sdram", 0,
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Subsignal("a", Pins(
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"A9 E10 B12 D13 C12 D11 D10 E9",
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"D9 B7 C8")),
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Subsignal("dq", Pins(
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"B13 A11 B9 C11 C9 C10 E8 B5",
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"B6 A6 A5 B4 C3 B3 B2 A2",
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"E2 E4 D3 E5 A4 D4 C4 D5",
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"D6 E6 D8 A8 B8 B10 B11 E11")),
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Subsignal("we_n", Pins("C7")),
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Subsignal("ras_n", Pins("D7")),
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Subsignal("cas_n", Pins("E7")),
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#Subsignal("cs_n", Pins("")), # gnd
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#Subsignal("cke", Pins("")), # 3v3
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Subsignal("ba", Pins("A7")),
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#Subsignal("dm", Pins("")), # gnd
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IOStandard("LVCMOS33"),
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Misc("SLEWRATE=FAST")
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),
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# ethernet (B50612D)
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("eth_clocks", 0,
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Subsignal("tx", Pins("M2")),
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Subsignal("rx", Pins("M1")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("P5")),
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Subsignal("mdio", Pins("T2")),
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Subsignal("mdc", Pins("P3")),
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Subsignal("rx_ctl", Pins("N6")),
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Subsignal("rx_data", Pins("N1 M5 N5 M6")),
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Subsignal("tx_ctl", Pins("M3")),
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Subsignal("tx_data", Pins("L1 L3 P2 L4")),
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IOStandard("LVCMOS33")
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),
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("eth_clocks", 1,
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Subsignal("tx", Pins("M12")),
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Subsignal("rx", Pins("M16")),
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IOStandard("LVCMOS33")
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),
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("eth", 1,
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Subsignal("rst_n", Pins("P5")),
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Subsignal("mdio", Pins("T2")),
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Subsignal("mdc", Pins("P3")),
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Subsignal("rx_ctl", Pins("L15")),
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Subsignal("rx_data", Pins("P13 N13 P14 M15")),
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Subsignal("tx_ctl", Pins("R15")),
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Subsignal("tx_data", Pins("T14 R12 R13 R14")),
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IOStandard("LVCMOS33")
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),
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]
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# from https://github.com/q3k/chubby75/blob/master/5a-75b/hardware_V7.1.md
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_connectors_v7_1 = [
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("j1", "F3 F1 G3 - G2 H3 H5 F15 L2 K1 J5 K2 B16 J14 F12 -"),
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("j2", "G4 G5 J2 - H2 J1 J3 F15 L2 K1 J5 K2 B16 J14 F12 -"),
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("j3", "J4 K3 G1 - K4 C2 E3 F15 L2 K1 J5 K2 B16 J14 F12 -"),
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("j4", "C1 A3 F4 - E1 F5 D1 F15 L2 K1 J5 K2 B16 J14 F12 -"),
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("j5", "H4 K5 P1 - R1 L5 F2 F15 L2 K1 J5 K2 B16 J14 F12 -"),
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("j6", "N3 M4 T4 - R5 R3 N4 F15 L2 K1 J5 K2 B16 J14 F12 -"),
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("j7", "P4 R2 M8 - M9 T6 R6 F15 L2 K1 J5 K2 B16 J14 F12 -"),
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("j8", "R8 R7 P8 - P7 N7 M7 F15 L2 K1 J5 K2 B16 J14 F12 -"),
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("j9", "M11 N11 P12 - K15 N12 L16 F15 L2 K1 J5 K2 B16 J14 F12 -"),
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("j10", "T13 N14 M14 - P16 T15 L14 F15 L2 K1 J5 K2 B16 J14 F12 -"),
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("j11", "K16 J15 J16 - J12 H15 G16 F15 L2 K1 J5 K2 B16 J14 F12 -"),
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("j12", "P15 L12 L13 - D14 R16 E16 F15 L2 K1 J5 K2 B16 J14 F12 -"),
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("j13", "H13 J13 H12 - G14 H14 G15 F15 L2 K1 J5 K2 B16 J14 F12 -"),
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("j14", "E14 D16 C15 - B15 C16 C14 F15 L2 K1 J5 K2 B16 J14 F12 -"),
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("j15", "A15 F16 A14 - E13 B14 A13 F15 L2 K1 J5 K2 B16 J14 F12 -"),
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("j16", "G13 G12 E15 - F14 F13 C13 F15 L2 K1 J5 K2 B16 J14 F12 -"),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk25"
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default_clk_period = 1e9/25e6
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def __init__(self, revision="7.1"):
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assert revision in ["7.1"]
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self.revision = revision
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device = {"7.1": "LFE5U-25F-6BG256C"}[revision]
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io = {"7.1": _io_v7_1}[revision]
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connectors = {"7.1": _connectors_v7_1}[revision]
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LatticePlatform.__init__(self, device, io, connectors=connectors, toolchain="trellis")
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def create_programmer(self):
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return OpenOCDJTAGProgrammer("openocd_colorlight_5a_75b.cfg")
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def do_finalize(self, fragment):
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LatticePlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/25e6)
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self.add_period_constraint(self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9/125e6)
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self.add_period_constraint(self.lookup_request("eth_clocks:rx", 1, loose=True), 1e9/125e6)
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@ -30,6 +30,9 @@
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# ./colorlight_5a_75b.py --load
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# You should see the LiteX BIOS and be able to interact with it.
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#
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# Note that you can also use a 5A-75E board:
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# ./colorlight_5a_75b.py --board=5A-75E --revision=7.1
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#
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# Disclaimer: SoC 2) is still a Proof of Concept with large timings violations on the IP/UDP and
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# Etherbone stack that need to be optimized. It was initially just used to validate the reversed
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# pinout but happens to work on hardware...
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@ -43,7 +46,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.io import DDROutput
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from litex_boards.platforms import colorlight_5a_75b
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from litex_boards.platforms import colorlight_5a_75b, colorlight_5a_75e
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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@ -92,8 +95,13 @@ class _CRG(Module):
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, revision, with_ethernet=False, with_etherbone=False, sys_clk_freq=60e6, **kwargs):
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def __init__(self, board, revision, with_ethernet=False, with_etherbone=False, sys_clk_freq=60e6, **kwargs):
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assert board in ["5A-75B", "5A-75E"]
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if board == "5A-75B":
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platform = colorlight_5a_75b.Platform(revision=revision)
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elif board == "5A-75E":
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platform = colorlight_5a_75e.Platform(revision=revision)
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if with_etherbone:
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sys_clk_freq = int(125e6)
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@ -138,6 +146,7 @@ def main():
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trellis_args(parser)
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--board", default="5A-75B", help="Board type: 5A-75B (default) or 5A-75E")
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parser.add_argument("--revision", default="7.0", type=str, help="Board revision 7.0 (default) or 6.1")
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parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
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parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
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@ -146,7 +155,7 @@ def main():
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args = parser.parse_args()
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assert not (args.with_ethernet and args.with_etherbone)
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soc = BaseSoC(revision=args.revision,
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soc = BaseSoC(board=args.board, revision=args.revision,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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sys_clk_freq = args.sys_clk_freq,
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