enjoy-digital
GitHub
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# This file is Copyright (c) 2019 Arnaud Durand <arnaud.durand@unifr.ch>
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# License: BSD
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("clk12", 0, Pins("A10"), IOStandard("LVCMOS33")),
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("rst_n", 0, Pins("G2"), IOStandard("LVCMOS33")),
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("user_led", 0, Pins("A13"), IOStandard("LVCMOS25")),
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("user_led", 1, Pins("A12"), IOStandard("LVCMOS25")),
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("user_led", 2, Pins("B19"), IOStandard("LVCMOS25")),
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("user_led", 3, Pins("A18"), IOStandard("LVCMOS25")),
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("user_led", 4, Pins("B18"), IOStandard("LVCMOS25")),
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("user_led", 5, Pins("C17"), IOStandard("LVCMOS25")),
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("user_led", 6, Pins("A17"), IOStandard("LVCMOS25")),
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("user_led", 7, Pins("B17"), IOStandard("LVCMOS25")),
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("user_dip_btn", 1, Pins("J1"), IOStandard("LVCMOS33")),
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("user_dip_btn", 2, Pins("H1"), IOStandard("LVCMOS33")),
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("user_dip_btn", 3, Pins("K1"), IOStandard("LVCMOS33")),
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("user_dip_btn", 4, Pins("E15"), IOStandard("LVCMOS25")),
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("user_dip_btn", 5, Pins("D16"), IOStandard("LVCMOS25")),
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("user_dip_btn", 6, Pins("B16"), IOStandard("LVCMOS25")),
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("user_dip_btn", 7, Pins("C16"), IOStandard("LVCMOS25")),
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("user_dip_btn", 8, Pins("A16"), IOStandard("LVCMOS25")),
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("serial", 0,
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Subsignal("rx", Pins("P2"), IOStandard("LVCMOS33")),
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Subsignal("tx", Pins("P3"), IOStandard("LVCMOS33")),
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),
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("clk200", 0,
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Subsignal("p", Pins("Y19")),
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Subsignal("n", Pins("W20")),
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IOStandard("LVDS")
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),
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("ext_clk50", 0, Pins("B11"), IOStandard("LVCMOS33")),
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("ext_clk50_en", 0, Pins("C11"), IOStandard("LVCMOS33")),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("RASP",
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"None", # (no pin 0)
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"None", # 1 3.3V
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"None", # 2 5V
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"T17", # 3 RASP_IO02
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"None", # 4 5V
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"U16", # 5 RASP_IO03
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"None", # 6 GND
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"U17", # 7 RASP_IO04
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"P18", # 8 RASP_IO14
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"None", # 9 GND
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"N20", # 10 RASP_IO15
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"N19", # 11 RASP_IO17
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"T16", # 12 RASP_IO18
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"M18", # 13 RASP_IO27
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"None", # 14 GND
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"N17", # 15 RASP_IO22
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"P17", # 16 RASP_IO23
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"None", # 17 3.3V
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"M17", # 18 RASP_IO24
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"U20", # 19 RASP_IO10
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"None", # 20 GND
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"T19", # 21 RASP_IO09
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"N18", # 22 RASP_IO25
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"R20", # 23 RASP_IO11
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"U19", # 24 RASP_IO08
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"None", # 25 GND
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"R18", # 26 RASP_IO07
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"L18", # 27 RASP_ID_SD
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"L17", # 28 RASP_ID_SC
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"U18", # 29 RASP_IO05
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"None", # 30 GND
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"T18", # 31 RASP_IO06
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"T20", # 32 RASP_IO12
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"P20", # 33 RASP_IO13
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"None", # 34 GND
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"R17", # 35 RASP_IO19
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"P19", # 36 RASP_IO16
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"N16", # 37 RASP_IO26
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"P16", # 38 RASP_IO20
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"None", # 39 GND
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"R16", # 40 RASP_IO21
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),
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("PMOD",
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"None", # (no pin 0)
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"C6", # 1
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"C7", # 2
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"E8", # 3
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"D8", # 4
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"None", # 5 GND
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"None", # 6 VCCIO0
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"C8", # 7 EXPCON_IO32
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"B8", # 8 EXPCON_IO33
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"A7", # 9 EXPCON_IO34
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"A8", # 10 EXPCON_IO35
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"None", # 11 GND
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"None", # 12 VCCIO0
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk12"
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default_clk_period = 1e9/12e6
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def __init__(self, **kwargs):
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LatticePlatform.__init__(self, "LFE5UM5G-85F-8BG381", _io, _connectors, **kwargs)
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def request(self, *args, **kwargs):
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if "serial" in args:
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print("two 0 Ω resistors shoud be populated on R34 and R35 and "
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"the FT2232H should be configured to UART with virtual COM on "
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"port B")
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if "ext_clk50" in args:
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print("an oscillator must be populated on X5")
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return LatticePlatform.request(self, *args, **kwargs)
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def create_programmer(self):
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pass
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# fdir = os.path.join(
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# os.path.abspath(os.path.dirname(__file__)), "prog")
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# return OpenOCD(os.path.join(fdir, "ecp5-evn.cfg"))
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@ -0,0 +1,80 @@
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#!/usr/bin/env python3
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# This file is Copyright (c) 2019 Arnaud Durand <arnaud.durand@unifr.ch>
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# License: BSD
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.community.platforms import ecp5_evn
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, x5_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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self.cd_sys.clk.attr.add("keep")
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# clk / rst
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clk = clk12 = platform.request("clk12")
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rst_n = platform.request("rst_n")
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platform.add_period_constraint(clk12, 1e9/12e6)
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if x5_clk_freq is not None:
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clk = clk50 = platform.request("ext_clk50")
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self.comb += platform.request("ext_clk50_en").eq(1)
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platform.add_period_constraint(clk50, 1e9/x5_clk_freq)
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# pll
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self.submodules.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(~rst_n)
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pll.register_clkin(clk, x5_clk_freq or 12e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n)
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self.comb += self.cd_sys.clk.eq(clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), x5_clk_freq=None, toolchain="diamond", **kwargs):
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platform = ecp5_evn.Platform(toolchain=toolchain)
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
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integrated_rom_size=0x8000,
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**kwargs)
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# crg
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crg = _CRG(platform, sys_clk_freq, x5_clk_freq)
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self.submodules.crg = crg
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on ECP5 Evaluation Board")
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parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond",
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help='gateware toolchain to use, diamond (default) or trellis')
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builder_args(parser)
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soc_core_args(parser)
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parser.add_argument("--sys-clk-freq", default=60e6,
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help="system clock frequency (default=60MHz)")
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parser.add_argument("--x5-clk-freq", type=int,
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help="use X5 oscillator as system clock at the specified frequency")
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args = parser.parse_args()
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cls = BaseSoC
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soc = cls(toolchain=args.toolchain,
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sys_clk_freq=int(float(args.sys_clk_freq)),
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x5_clk_freq=args.x5_clk_freq,
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**soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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