adding colognechip_gatemate_evb
This commit is contained in:
Gwenhael Goavec-Merou
Gwenhael Goavec-Merou
parent
33a0975dd7
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Gwenhael Goavec-merou<gwenhael.goavec-merou@trabucayre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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# Board documentation/schematics:
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# https://colognechip.com/docs/ds1003-gatemate1-evalboard-3v1-latest.pdf
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from litex.build.generic_platform import *
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from litex.build.colognechip.platform import CologneChipPlatform
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk10", 0, Pins("IO_SB_A8"), Misc("SCHMITT_TRIGGER=true")),
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# Leds
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("user_led_n", 0, Pins("IO_EB_B1")),
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("user_led_n", 1, Pins("IO_EB_B2")),
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("user_led_n", 2, Pins("IO_EB_B3")),
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("user_led_n", 3, Pins("IO_EB_B4")),
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("user_led_n", 4, Pins("IO_EB_B5")),
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("user_led_n", 5, Pins("IO_EB_B6")),
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("user_led_n", 6, Pins("IO_EB_B7")),
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("user_led_n", 7, Pins("IO_EB_B8")),
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# Button
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("user_btn_n", 0, Pins("IO_EB_B0")),
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# SPIFlash
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("spiflash", 0,
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Subsignal("cs_n", Pins("IO_WA_A8")),
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Subsignal("clk", Pins("IO_WA_B8")),
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Subsignal("miso", Pins("IO_WA_B7")),
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Subsignal("mosi", Pins("IO_WA_A7")),
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Subsignal("wp", Pins("IO_WA_B6")),
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Subsignal("hold", Pins("IO_WA_B6")),
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("IO_WA_A8")),
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Subsignal("clk", Pins("IO_WA_B8")),
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Subsignal("dq", Pins("IO_WA_B7 IO_WA_A7 IO_WA_B6 IO_WA_B6")),
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),
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# HyperRAM
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("hyperram", 0,
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Subsignal("dq", Pins("IO_WB_A5 IO_WB_B5 IO_WB_A6 IO_WB_B6 IO_WB_A7 IO_WB_B7 IO_WB_A8 IO_WB_B8")),
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Subsignal("rwds", Pins("IO_WB_B4")),
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Subsignal("cs_n", Pins("IO_WB_B0")),
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Subsignal("rst_n", Pins("IO_WB_A2")),
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Subsignal("clk_p", Pins("IO_WB_A3")),
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Subsignal("clk_n", Pins("IO_WB_B3")),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("PMODA", "IO_NB_A0 IO_NB_A1 IO_NB_A2 IO_NB_A3 IO_NB_B0 IO_NB_B1 IO_NB_B2 IO_NB_B3"),
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("PMODB", "IO_NB_A4 IO_NB_A5 IO_NB_A6 IO_NB_A7 IO_NB_B4 IO_NB_B5 IO_NB_B6 IO_NB_B7"),
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("io_na", "IO_NA_A0 IO_NA_B0",
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"IO_NA_A1 IO_NA_B1",
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"IO_NA_A2 IO_NA_B2",
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"IO_NA_A3 IO_NA_B3",
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"IO_NA_A4 IO_NA_B4",
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"IO_NA_A5 IO_NA_B5",
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"IO_NA_A6 IO_NA_B6",
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"IO_NA_A7 IO_NA_B7",
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"IO_NA_A8 IO_NA_B8"),
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("io_nb", "IO_NB_A4 IO_NB_A5",
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"IO_NB_A6 IO_NB_A7",
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"IO_NB_B4 IO_NB_B5",
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"IO_NB_B6 IO_NB_B7"),
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("io_ea", "IO_EA_A0 IO_EA_B0",
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"IO_EA_A1 IO_EA_B1",
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"IO_EA_A2 IO_EA_B2",
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"IO_EA_A3 IO_EA_B3",
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"IO_EA_A4 IO_EA_B4",
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"IO_EA_A5 IO_EA_B5",
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"IO_EA_A6 IO_EA_B6",
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"IO_EA_A7 IO_EA_B7",
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"IO_EA_A8 IO_EA_B8"),
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("io_sa", "IO_SA_A0 IO_SA_B0",
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"IO_SA_A1 IO_SA_B1",
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"IO_SA_A2 IO_SA_B2",
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"IO_SA_A3 IO_SA_B3",
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"IO_SA_A4 IO_SA_B4",
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"IO_SA_A5 IO_SA_B5",
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"IO_SA_A6 IO_SA_B6",
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"IO_SA_A7 IO_SA_B7",
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"IO_SA_A8 IO_SA_B8"),
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("io_sb", "IO_SB_A0 IO_SB_B0",
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"IO_SB_A1 IO_SB_B1",
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"IO_SB_A2 IO_SB_B2",
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"IO_SB_A3 IO_SB_B3",
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"IO_SB_A4 IO_SB_B4",
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"IO_SB_A5 IO_SB_B5",
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"IO_SB_A6 IO_SB_B6",
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"IO_SB_A7 IO_SB_B7",
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"IO_SB_A8 IO_SB_B8"),
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("io_wc", "IO_WC_A0 IO_WC_B0",
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"IO_WC_A1 IO_WC_B1",
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"IO_WC_A2 IO_WC_B2",
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"IO_WC_A3 IO_WC_B3",
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"IO_WC_A4 IO_WC_B4",
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"IO_WC_A5 IO_WC_B5",
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"IO_WC_A6 IO_WC_B6",
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"IO_WC_A7 IO_WC_B7",
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"IO_WC_A8 IO_WC_B8"),
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]
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# PMODS --------------------------------------------------------------------------------------------
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def usb_pmod_io(pmod):
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return [
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# USB-UART PMOD: https://store.digilentinc.com/pmod-usbuart-usb-to-uart-interface/
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("usb_uart", 0,
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Subsignal("tx", Pins(f"{pmod}:1")),
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Subsignal("rx", Pins(f"{pmod}:2")),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(CologneChipPlatform):
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default_clk_name = "clk10"
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default_clk_period = 1e9/10e6
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def __init__(self, toolchain="colognechip"):
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CologneChipPlatform.__init__(self, "CCGM1A1", _io, _connectors, toolchain=toolchain)
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def create_programmer(self):
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return OpenFPGALoader("gatemate_evb_jtag")
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def do_finalize(self, fragment):
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CologneChipPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk10", loose=True), 1e9/10e6)
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@ -0,0 +1,97 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Gwenhael Goavec-merou<gwenhael.goavec-merou@trabucayre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import colognechip_gatemate_evb
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from litex.build.io import CRG
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from litex.soc.cores.clock.colognechip import GateMatePLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.build.generic_platform import Pins
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from litex.soc.cores.led import LedChaser
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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rst_n = Signal()
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self.cd_sys = ClockDomain()
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# # #
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# Clk / Rst
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clk10 = platform.request("clk10")
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self.rst = ~platform.request("user_btn_n", 0)
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self.specials += Instance("CC_USR_RSTN", o_USR_RSTN = rst_n)
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# PLL
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self.pll = pll = GateMatePLL(perf_mode="economy")
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self.comb += pll.reset.eq(~rst_n | self.rst)
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pll.register_clkin(clk10, 10e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=48e6,
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with_led_chaser = True,
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**kwargs):
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platform = colognechip_gatemate_evb.Platform()
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# USBUART PMOD as Serial--------------------------------------------------------------------
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platform.add_extension(colognechip_gatemate_evb.usb_pmod_io("PMODB"))
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kwargs["uart_name"] = "usb_uart"
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on GateMate EVB", **kwargs)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led_n"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=colognechip_gatemate_evb.Platform, description="LiteX SoC on Gatemate EVB")
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parser.add_target_argument("--sys-clk-freq", default=24e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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**parser.soc_argdict)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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from litex.build.openfpgaloader import OpenFPGALoader
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prog = OpenFPGALoader("gatemate_evb_spi")
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prog.flash(0, builder.get_bitstream_filename(mode="flash"))
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if __name__ == "__main__":
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main()
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@ -19,6 +19,7 @@ class TestTargets(unittest.TestCase):
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"qmtech_rp2040_daughterboard", # Reason: Not a real platform.
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"enclustra_st1", # Readon: Not a real platform.
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"quicklogic_quickfeather", # Reason: No default clock.
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"colognechip_gatemate_evb", # Reason: toolchain not yet mainlined
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"efinix_titanium_ti60_f225_dev_kit", # Reason: Require Efinity toolchain.
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"efinix_trion_t120_bga576_dev_kit", # Reason: Require Efinity toolchain.
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"efinix_trion_t20_bga256_dev_kit", # Reason: Require Efinity toolchain.
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@ -33,6 +34,7 @@ class TestTargets(unittest.TestCase):
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excluded_targets = [
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"simple", # Reason: Generic target.
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"quicklogic_quickfeather", # Reason: No default clock.
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"colognechip_gatemate_evb", # Reason: toolchain not yet mainlined
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"efinix_titanium_ti60_f225_dev_kit", # Reason: Require Efinity toolchain.
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"efinix_trion_t120_bga576_dev_kit", # Reason: Require Efinity toolchain.
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"efinix_trion_t20_bga256_dev_kit", # Reason: Require Efinity toolchain.
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