Merge pull request #294 from antmicro/fix-ddr4-datacenter-platform

platforms: ddr4 datacenter: invert eth clocks
2021-11-21 19:11:13 +01:00 · 2021-11-21 19:11:13 +01:00 · b1817af8a8
parent 3e9e9bc425 fa26b126df
commit b1817af8a8
1 changed files with 2 additions and 2 deletions
--- a/litex_boards/platforms/antmicro_datacenter_ddr4_test_board.py
+++ b/litex_boards/platforms/antmicro_datacenter_ddr4_test_board.py
@ -82,8 +82,8 @@ _io = [
    # RGMII Ethernet
    ("eth_ref_clk", 0, Pins("AA23"), IOStandard("LVCMOS33")),
    ("eth_clocks", 0,
-        Subsignal("tx", Pins("Y23")),
-        Subsignal("rx", Pins("AA24")),
+        Subsignal("rx", Pins("Y23")),
+        Subsignal("tx", Pins("AA24")),
        IOStandard("LVCMOS33")
    ),
    ("eth", 0,