Add CrossLink-NX VIP board platform and target
This commit is contained in:
David Shah
parent
8e5b31646d
commit
b278d8bccc
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 David Corrigan <davidcorrigan714@gmail.com>
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# Copyright (c) 2020 Alan Green <avg@google.com>
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# Copyright (c) 2020 David Shah <dave@ds0.me>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice.programmer import LatticeProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("clk12", 0, Pins("L16"), IOStandard("LVCMOS33")), # Ensure JP2 is installed
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# Reference clocks. Why are there four 27MHz oscs. Is this really correct??
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("clk27_0", 0, Pins("L5"), IOStandard("LVCMOS18")),
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("clk27_1", 0, Pins("L7"), IOStandard("LVCMOS18")),
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("clk27_2", 0, Pins("M2"), IOStandard("LVCMOS18")),
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("clk27_3", 0, Pins("Y2"), IOStandard("LVCMOS18")),
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# 8.1. General Purpose Push Buttons - all logic zero when pressed]
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("cam_reset", 0, Pins("T1"), IOStandard("LVCMOS18")), # SW1
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("gsrn", 0, Pins("G13"), IOStandard("LVCMOS33")), # SW3
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("programn", 0, Pins("E11"), IOStandard("LVCMOS33")), # SW4
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("user_btn", 0, Pins("L20"), IOStandard("LVCMOS33")), # SW5
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("user_btn", 1, Pins("L19"), IOStandard("LVCMOS33")), # SW6
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("serial", 0,
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Subsignal("rx", Pins("F14"), IOStandard("LVCMOS33")),
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Subsignal("tx", Pins("F16"), IOStandard("LVCMOS33")),
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),
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# Section 7.1 Status LEDs
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("user_led", 0, Pins("G14"), IOStandard("LVCMOS33")), # Green
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("user_led", 1, Pins("G15"), IOStandard("LVCMOS33")), # Green
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("user_led", 2, Pins("L13"), IOStandard("LVCMOS33")), # Green
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("user_led", 3, Pins("L14"), IOStandard("LVCMOS33")), # Green
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# Section 8.1 DIP Switch
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("user_dip_btn", 0, Pins("R5"), IOStandard("LVCMOS18")),
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("user_dip_btn", 1, Pins("R6"), IOStandard("LVCMOS18")),
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("user_dip_btn", 2, Pins("Y5"), IOStandard("LVCMOS18")),
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("user_dip_btn", 3, Pins("W5"), IOStandard("LVCMOS18")),
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# SPI Flash
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("spiflash", 0,
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Subsignal("cs_n", Pins("E13")),
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Subsignal("clk", Pins("E12")),
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Subsignal("mosi", Pins("D13")),
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Subsignal("miso", Pins("D15")),
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Subsignal("wp", Pins("D14")),
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Subsignal("hold", Pins("D16")),
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IOStandard("LVCMOS33")
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("E13")),
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Subsignal("clk", Pins("E12")),
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Subsignal("dq", Pins("D13 D15 D14 D16")),
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IOStandard("LVCMOS33")
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),
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# Camera I2C buses
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("i2c", 0,
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Subsignal("sda", Pins("N4")),
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Subsignal("scl", Pins("N5")),
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IOStandard("LVCMOS18")
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),
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("i2c", 1,
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Subsignal("sda", Pins("N6")),
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Subsignal("scl", Pins("N7")),
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IOStandard("LVCMOS18")
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),
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("i2c", 2,
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Subsignal("sda", Pins("P1")),
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Subsignal("scl", Pins("P2")),
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IOStandard("LVCMOS18")
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),
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("i2c", 3,
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Subsignal("sda", Pins("P5")),
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Subsignal("scl", Pins("P6")),
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IOStandard("LVCMOS18")
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),
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# Shared camera control signals
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("cam_ctrl",
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Subsignal("cam_reset", Pins("T1")),
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Subsignal("cam_frame_sync", Pins("U1")),
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),
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# MIPI camera modules
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# Note that use of MIPI_DPHY standard for + and LVCMOS12H for - is copied from Lattice PDC
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("camera", 0,
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Subsignal("mclk", Pins("M3"), IOStandard("LVCMOS18")),
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Subsignal("clkp", Pins("A2"), IOStandard("MIPI_DPHY")),
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Subsignal("clkn", Pins("B1"), IOStandard("LVCMOS12H")),
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Subsignal("dp", Pins("B2 A3 C2 A4"), IOStandard("MIPI_DPHY")),
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Subsignal("dn", Pins("C1 B3 D1 B4"), IOStandard("LVCMOS12H")),
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),
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("camera", 1,
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Subsignal("mclk", Pins("M4"), IOStandard("LVCMOS18")),
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Subsignal("clkp", Pins("A8"), IOStandard("MIPI_DPHY")),
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Subsignal("clkn", Pins("B8"), IOStandard("LVCMOS12H")),
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Subsignal("dp", Pins("A7 A9 A6 A10"), IOStandard("MIPI_DPHY")),
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Subsignal("dn", Pins("B7 B9 B6 B10"), IOStandard("LVCMOS12H")),
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),
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("camera", 2,
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Subsignal("mclk", Pins("M5"), IOStandard("LVCMOS18")),
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Subsignal("clkp", Pins("W11"), IOStandard("MIPI_DPHY")),
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Subsignal("clkn", Pins("Y11"), IOStandard("LVCMOS12H")),
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Subsignal("dp", Pins("V11 W13 U12 R12"), IOStandard("MIPI_DPHY")),
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Subsignal("dn", Pins("U11 V12 T12 P12"), IOStandard("LVCMOS12H")),
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),
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("camera", 3,
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Subsignal("mclk", Pins("M6"), IOStandard("LVCMOS18")),
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Subsignal("clkp", Pins("T13"), IOStandard("MIPI_DPHY")),
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Subsignal("clkn", Pins("T14"), IOStandard("LVCMOS12H")),
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Subsignal("dp", Pins("Y15 U15 V17 P13"), IOStandard("MIPI_DPHY")),
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Subsignal("dn", Pins("Y16 V16 U16 R13"), IOStandard("LVCMOS12H")),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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# Link to ECP5
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("UPSTREAM", {
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"D0": "N14",
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"D1": "M14",
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"D2": "M16",
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"D3": "M15",
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"D4": "N15",
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"D5": "N16",
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"D6": "M17",
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"D7": "M18",
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"D8": "M19",
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"D9": "M20",
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"D10": "N19",
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"D11": "N20",
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"D12": "P19",
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"D13": "P20",
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"D14": "P17",
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"D15": "P18",
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"D16": "R17",
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"D17": "R18",
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"D18": "U20",
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"D19": "T20",
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"D20": "W20",
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"D21": "V20",
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"D22": "T18",
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"D23": "U18",
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"D24": "V18",
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"D25": "V19",
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"D26": "W19",
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"PCLK_DOWN": "Y19",
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"GSRN": "G13",
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"SDA": "E20",
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"SCL": "F20",
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"UP_GPIO39": "F18",
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"UP_GPIO40": "G19",
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"UP_GPIO41": "L15",
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"UP_GPIO42": "D17",
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}
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),
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# PMOD signal number:
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# 1 2 3 4 7 8 9 10
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("PMOD0", "D10 D9 D7 D8 D6 D5 D4 D3"),
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("PMOD1", "E10 E9 E7 E8 E4 E3 E2 F1"),
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("PMOD2", "J2 J1 K2 K1 K3 K4 E17 F13"),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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def __init__(self, device="LIFCL", **kwargs):
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assert device in ["LIFCL"]
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LatticePlatform.__init__(self, device + "-40-9BG400C", _io, _connectors, toolchain="radiant", **kwargs)
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def create_programmer(self, mode = "direct"):
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assert mode in ["direct","flash"]
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xcf_template_direct = """<?xml version='1.0' encoding='utf-8' ?>
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<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
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<ispXCF version="R1.2.0">
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<Comment></Comment>
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<Chain>
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<Comm>JTAG</Comm>
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<Device>
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<SelectedProg value="TRUE"/>
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<Pos>1</Pos>
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<Vendor>Lattice</Vendor>
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<Family>LIFCL</Family>
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<Name>LIFCL-40</Name>
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<IDCode>0x010f1043</IDCode>
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<Package>All</Package>
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<PON>LIFCL-40</PON>
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<Bypass>
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<InstrLen>8</InstrLen>
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<InstrVal>11111111</InstrVal>
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<BScanLen>1</BScanLen>
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<BScanVal>0</BScanVal>
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</Bypass>
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<File>{bitstream_file}</File>
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<JedecChecksum>N/A</JedecChecksum>
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<MemoryType>Static Random Access Memory (SRAM)</MemoryType>
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<Operation>Fast Configuration</Operation>
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<Option>
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<SVFVendor>JTAG STANDARD</SVFVendor>
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<IOState>HighZ</IOState>
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<PreloadLength>362</PreloadLength>
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<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
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<Usercode>0x00000000</Usercode>
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<AccessMode>Direct Programming</AccessMode>
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</Option>
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</Device>
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</Chain>
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<ProjectOptions>
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<Program>SEQUENTIAL</Program>
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<Process>ENTIRED CHAIN</Process>
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<OperationOverride>No Override</OperationOverride>
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<StartTAP>TLR</StartTAP>
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<EndTAP>TLR</EndTAP>
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<VerifyUsercode value="FALSE"/>
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<TCKDelay>3</TCKDelay>
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</ProjectOptions>
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<CableOptions>
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<CableName>USB2</CableName>
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<PortAdd>FTUSB-0</PortAdd>
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</CableOptions>
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</ispXCF>
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"""
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xcf_template_flash = """<?xml version='1.0' encoding='utf-8' ?>
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<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
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<ispXCF version="R1.2.0">
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<Comment></Comment>
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<Chain>
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<Comm>JTAG2SPI</Comm>
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<Device>
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<SelectedProg value="TRUE"/>
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<Pos>1</Pos>
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<Vendor>Lattice</Vendor>
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<Family>LIFCL</Family>
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<Name>LIFCL-40</Name>
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<Package>All</Package>
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<Bypass>
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<InstrLen>8</InstrLen>
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<InstrVal>11111111</InstrVal>
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<BScanLen>1</BScanLen>
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<BScanVal>0</BScanVal>
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</Bypass>
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<File>{bitstream_file}</File>
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<MemoryType>External SPI Flash Memory (SPI FLASH)</MemoryType>
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<Operation>Erase,Program,Verify</Operation>
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<Option>
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<SVFVendor>JTAG STANDARD</SVFVendor>
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<Usercode>0x00000000</Usercode>
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<AccessMode>Direct Programming</AccessMode>
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</Option>
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<FPGALoader>
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<CPLDDevice>
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<Device>
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<Pos>1</Pos>
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<Vendor>Lattice</Vendor>
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<Family>LIFCL</Family>
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<Name>LIFCL-40</Name>
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<IDCode>0x010f1043</IDCode>
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<Package>All</Package>
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<PON>LIFCL-40</PON>
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<Bypass>
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<InstrLen>8</InstrLen>
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<InstrVal>11111111</InstrVal>
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<BScanLen>1</BScanLen>
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<BScanVal>0</BScanVal>
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</Bypass>
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<MemoryType>Static Random Access Memory (SRAM)</MemoryType>
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<Operation>Refresh Verify ID</Operation>
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<Option>
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<SVFVendor>JTAG STANDARD</SVFVendor>
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<IOState>HighZ</IOState>
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<PreloadLength>362</PreloadLength>
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<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
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<AccessMode>Direct Programming</AccessMode>
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</Option>
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</Device>
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</CPLDDevice>
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<FlashDevice>
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<Device>
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<Pos>1</Pos>
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<Vendor>Macronix</Vendor>
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<Family>SPI Serial Flash</Family>
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<Name>MX25L12833F</Name>
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<IDCode>0x18</IDCode>
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<Package>8-pin SOP</Package>
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<Operation>Erase,Program,Verify</Operation>
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<File>{bitstream_file}</File>
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<AddressBase>0x00000000</AddressBase>
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<EndAddress>0x000F0000</EndAddress>
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<DeviceSize>128</DeviceSize>
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<DataSize>1016029</DataSize>
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<NumberOfDevices>1</NumberOfDevices>
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<ReInitialize value="FALSE"/>
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</Device>
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</FlashDevice>
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<FPGADevice>
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<Device>
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<Pos>1</Pos>
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<Name></Name>
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<File>{bitstream_file}</File>
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<LocalChainList>
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<LocalDevice index="-99"
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name="Unknown"
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file="{bitstream_file}"/>
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</LocalChainList>
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<Option>
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<SVFVendor>JTAG STANDARD</SVFVendor>
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</Option>
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</Device>
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</FPGADevice>
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</FPGALoader>
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</Device>
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</Chain>
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<ProjectOptions>
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<Program>SEQUENTIAL</Program>
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<Process>ENTIRED CHAIN</Process>
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<OperationOverride>No Override</OperationOverride>
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<StartTAP>TLR</StartTAP>
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<EndTAP>TLR</EndTAP>
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<DisableCheckBoard value="TRUE"/>
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<VerifyUsercode value="FALSE"/>
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<TCKDelay>3</TCKDelay>
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</ProjectOptions>
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<CableOptions>
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<CableName>USB2</CableName>
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<PortAdd>FTUSB-0</PortAdd>
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<USBID>Lattice ECP5 VIP Processor Board 0000 Serial FT4RXXZ5</USBID>
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</CableOptions>
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</ispXCF>
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"""
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if mode == "direct":
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xcf_template = xcf_template_direct
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if mode == "flash":
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xcf_template = xcf_template_flash
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return LatticeProgrammer(xcf_template)
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@ -0,0 +1,116 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 David Corrigan <davidcorrigan714@gmail.com>
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# Copyright (c) 2020 Alan Green <avg@google.com>
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# Copyright (c) 2020 David Shah <dave@ds0.me>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import crosslink_nx_vip
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|
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from litex.soc.cores.nxlram import NXLRAM
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from litex.soc.cores.spi_flash import SpiFlash
|
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from litex.build.io import CRG
|
||||||
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from litex.build.generic_platform import *
|
||||||
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|
||||||
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
|
||||||
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from litex.soc.integration.builder import *
|
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from litex.soc.cores.led import LedChaser
|
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|
||||||
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kB = 1024
|
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|
mB = 1024*kB
|
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|
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||||||
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# CRG ----------------------------------------------------------------------------------------------
|
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|
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
|
||||||
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self.clock_domains.cd_sys = ClockDomain()
|
||||||
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self.clock_domains.cd_por = ClockDomain()
|
||||||
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|
||||||
|
# TODO: replace with PLL
|
||||||
|
# Clocking
|
||||||
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self.submodules.sys_clk = sys_osc = NXOSCA()
|
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sys_osc.create_hf_clk(self.cd_sys, sys_clk_freq)
|
||||||
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platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq)
|
||||||
|
rst_n = platform.request("gsrn")
|
||||||
|
|
||||||
|
# Power On Reset
|
||||||
|
por_cycles = 4096
|
||||||
|
por_counter = Signal(log2_int(por_cycles), reset=por_cycles-1)
|
||||||
|
self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
|
||||||
|
self.sync.por += If(por_counter != 0, por_counter.eq(por_counter - 1))
|
||||||
|
self.specials += AsyncResetSynchronizer(self.cd_por, ~rst_n)
|
||||||
|
self.specials += AsyncResetSynchronizer(self.cd_sys, (por_counter != 0))
|
||||||
|
|
||||||
|
|
||||||
|
# BaseSoC ------------------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
class BaseSoC(SoCCore):
|
||||||
|
SoCCore.mem_map = {
|
||||||
|
"rom": 0x00000000,
|
||||||
|
"sram": 0x40000000,
|
||||||
|
"csr": 0xf0000000,
|
||||||
|
}
|
||||||
|
def __init__(self, sys_clk_freq, **kwargs):
|
||||||
|
platform = crosslink_nx_vip.Platform()
|
||||||
|
|
||||||
|
platform.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}")
|
||||||
|
|
||||||
|
# Disable Integrated SRAM since we want to instantiate LRAM specifically for it
|
||||||
|
kwargs["integrated_sram_size"] = 0
|
||||||
|
|
||||||
|
# SoCCore -----------------------------------------_----------------------------------------
|
||||||
|
SoCCore.__init__(self, platform, sys_clk_freq,
|
||||||
|
ident = "LiteX SoC on Crosslink-NX VIP Input Board",
|
||||||
|
ident_version = True,
|
||||||
|
**kwargs)
|
||||||
|
|
||||||
|
# CRG --------------------------------------------------------------------------------------
|
||||||
|
self.submodules.crg = _CRG(platform, sys_clk_freq)
|
||||||
|
|
||||||
|
# 128KB LRAM (used as SRAM) ---------------------------------------------------------------
|
||||||
|
size = 128*kB
|
||||||
|
self.submodules.spram = NXLRAM(32, size)
|
||||||
|
self.register_mem("sram", self.mem_map["sram"], self.spram.bus, size)
|
||||||
|
|
||||||
|
# Leds -------------------------------------------------------------------------------------
|
||||||
|
self.submodules.leds = LedChaser(
|
||||||
|
pads = Cat(*[platform.request("user_led", i) for i in range(4)]),
|
||||||
|
sys_clk_freq = sys_clk_freq)
|
||||||
|
self.add_csr("leds")
|
||||||
|
|
||||||
|
|
||||||
|
# Build --------------------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
def main():
|
||||||
|
parser = argparse.ArgumentParser(description="LiteX SoC on Crosslink-NX Eval Board")
|
||||||
|
parser.add_argument("--build", action="store_true", help="Build bitstream")
|
||||||
|
parser.add_argument("--load", action="store_true", help="Load bitstream")
|
||||||
|
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default=75MHz)")
|
||||||
|
parser.add_argument("--prog-target", default="direct", help="Programming Target: direct or flash")
|
||||||
|
builder_args(parser)
|
||||||
|
soc_core_args(parser)
|
||||||
|
args = parser.parse_args()
|
||||||
|
|
||||||
|
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), **soc_core_argdict(args))
|
||||||
|
builder = Builder(soc, **builder_argdict(args))
|
||||||
|
builder_kargs = {}
|
||||||
|
builder.build(**builder_kargs, run=args.build)
|
||||||
|
|
||||||
|
if args.load:
|
||||||
|
prog = soc.platform.create_programmer(args.prog_target)
|
||||||
|
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
|
||||||
|
|
||||||
|
if __name__ == "__main__":
|
||||||
|
main()
|
||||||
Loading…
Reference in New Issue