di_adrv2crr_fmc: Bump PCIe to 8 lanes

There used to be an issue with 8 lanes litepcie USP for that board
when it was first added, but it's been solved now, so might as well
use all the available lanes

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

litex_boards/targets/adi_adrv2crr_fmc.py

@@ -93,9 +93,9 @@ class BaseSoC(SoCCore):
         if with_pcie:
             assert self.csr_data_width == 32
 
-            self.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"),
+            self.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x8"),
                 speed = "gen3",
-                data_width = 128,
+                data_width = 256,
                 bar0_size  = 0x20000)
             self.add_pcie(phy=self.pcie_phy, ndmas=1)