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di_adrv2crr_fmc: Bump PCIe to 8 lanes 

There used to be an issue with 8 lanes litepcie USP for that board
when it was first added, but it's been solved now, so might as well
use all the available lanes

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
This commit is contained in:
Sylvain Munaut 2024-02-05 11:43:02 +01:00
parent 2264df8a0a
commit b3caabcca3
1 changed files with 2 additions and 2 deletions
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4
litex_boards/targets/adi_adrv2crr_fmc.py
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@ -93,9 +93,9 @@ class BaseSoC(SoCCore):
if with_pcie: if with_pcie:
assert self.csr_data_width == 32 assert self.csr_data_width == 32
self.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"), self.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x8"),
speed = "gen3", speed = "gen3",
data_width = 128, data_width = 256,
bar0_size = 0x20000) bar0_size = 0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1) self.add_pcie(phy=self.pcie_phy, ndmas=1)