Merge pull request #309 from derekmulcahy/master
Initial release for Snickerdoodle
This commit is contained in:
enjoy-digital
GitHub
commit
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2021 Derek Mulcahy <derekmulcahy@gmail.com>,
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst - A placeholder for an external clock
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("clk100", 0, Pins("H16"), IOStandard("LVCMOS33")),
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# Leds - A placeholder for an external LED
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("user_led", 0, Pins("G14"), IOStandard("LVCMOS33")),
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# UART - A placeholder for an external UART
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("serial", 0,
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Subsignal("tx", Pins("D19")),
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Subsignal("rx", Pins("D20")),
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IOStandard("LVCMOS33"),
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),
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# PS7
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("ps7_clk", 0, Pins(1)),
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("ps7_porb", 0, Pins(1)),
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("ps7_srstb", 0, Pins(1)),
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("ps7_mio", 0, Pins(54)),
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("ps7_ddram", 0,
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Subsignal("addr", Pins(15)),
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Subsignal("ba", Pins(3)),
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Subsignal("cas_n", Pins(1)),
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Subsignal("ck_n", Pins(1)),
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Subsignal("ck_p", Pins(1)),
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Subsignal("cke", Pins(1)),
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Subsignal("cs_n", Pins(1)),
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Subsignal("dm", Pins(4)),
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Subsignal("dq", Pins(32)),
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Subsignal("dqs_n", Pins(4)),
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Subsignal("dqs_p", Pins(4)),
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Subsignal("odt", Pins(1)),
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Subsignal("ras_n", Pins(1)),
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Subsignal("reset_n", Pins(1)),
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Subsignal("we_n", Pins(1)),
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Subsignal("vrn", Pins(1)),
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Subsignal("vrp", Pins(1)),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("ja1", "- - - G14 E18 D20 E19 D19 - - F16 B20 F17 C20 - - E17 A20 D18 B19 - - F19 G20 F20 G19 - - J20 G18 H20 G17 - - J18 H17 H18 H16 - -"),
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("ja2", "- - - J15 L14 J16 L15 K16 - - M14 G15 M15 H15 - - N15 J14 N16 K14 - - L19 J19 L20 K19 - - M17 M20 M18 M19 - - L16 K18 L17 K17 - -"),
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("jb1", "- - - T19 T11 U12 T10 T12 - - P14 W13 R14 V12 - - U13 T14 V13 T14 - - T16 Y17 U17 Y16 - - W14 W15 Y14 V15 - - U14 U19 U15 U18 - -"),
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("jb2", "- - - R19 N17 P16 P18 P15 - - T17 R17 R18 R16 - - V17 W19 V18 W18 - - T20 W16 U20 V16 - - V20 Y19 W20 Y18 - - N20 P19 P20 N18 - -"),
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("jc1", "- - - V5 U7 U10 V7 T9 - - T5 Y13 U5 Y12 - - V11 W6 V10 V6 - - V8 Y11 W8 W11 - - U9 W9 U8 W10 - - Y9 Y6 Y8 Y7 - -"),
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# ("xadc", "N15 L14 K16 K14 N16 L15 J16 J14"),
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# ("mrcc", "H17 H16 K18 K17 U19 U18 P19 N18 Y6 Y7"),
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# ("srcc", "J18 H18 L16 L17 U14 U15 N20 P20 Y9 Y8"),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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# The clock speed depends on the PS7 PLL configuration for the FCLK_CLK0 signal.
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default_clk_name = "clk100"
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default_clk_freq = 100e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7z010-clg400-1", _io, _connectors, toolchain="vivado")
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self.default_clk_period = 1e9 / self.default_clk_freq
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def create_programmer(self):
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return VivadoProgrammer(flash_part="n25q128a")
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request(self.default_clk_name, loose=True),
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self.default_clk_period)
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>,
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# Copyright (c) 2021 Derek Mulcahy <derekmulcahy@gmail.com>,
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from litex_boards.platforms import snickerdoodle
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.interconnect import axi
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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# UTILS ---------------------------------------------------------------------------------------------
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def load_ps7(soc, xci_file):
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odir = os.path.join("build", "snickerdoodle", "gateware", "xci")
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os.makedirs(odir, exist_ok=True)
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file = "snickerdoodle_ps7.xci"
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dst = os.path.join(odir, file)
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if xci_file is None:
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src = "https://technicaltoys-support.s3.amazonaws.com/xci/" + file
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os.system("wget " + src + " -O " + dst)
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else:
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os.system("cp -p " + xci_file + " " + dst)
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soc.cpu.set_ps7_xci(dst)
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, use_ps7_clk=False):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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if use_ps7_clk:
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assert sys_clk_freq == 100e6
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self.comb += ClockSignal("sys").eq(ClockSignal("ps7"))
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self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst)
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else:
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self.submodules.pll = pll = S7MMCM(speedgrade=-1)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request(platform.default_clk_name),
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platform.default_clk_freq)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# Ignore sys_clk to pll.clkin path created by SoC's rst.
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self,
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sys_clk_freq = int(100e6),
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ext_clk_freq = None,
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with_led_chaser = True,
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xci_file = None,
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**kwargs):
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platform = snickerdoodle.Platform()
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if ext_clk_freq:
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platform.default_clk_freq = ext_clk_freq
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platform.default_clk_period = 1e9 / ext_clk_freq
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if kwargs.get("cpu_type", None) == "zynq7000":
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kwargs['integrated_sram_size'] = 0
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kwargs['with_uart'] = False
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self.mem_map = {
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'csr': 0x4000_0000, # Zynq GP0 default
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}
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Snickerdoodle",
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ident_version = True,
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**kwargs)
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# Zynq7000 Integration ---------------------------------------------------------------------
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if kwargs.get("cpu_type", None) == "zynq7000":
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load_ps7(self, xci_file)
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# Connect AXI GP0 to the SoC with base address of 0x43c00000 (default one)
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wb_gp0 = wishbone.Interface()
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self.submodules += axi.AXI2Wishbone(
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axi = self.cpu.add_axi_gp_master(),
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wishbone = wb_gp0,
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base_address = self.mem_map['csr'])
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self.add_wb_master(wb_gp0)
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use_ps7_clk = True
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else:
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use_ps7_clk = False
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, use_ps7_clk)
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platform.add_platform_command("set_property BITSTREAM.GENERAL.COMPRESS True [current_design]")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Snickerdoodle")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--ext-clk-freq", default=10e6, type=float, help="External Clock Frequency")
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parser.add_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency")
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parser.add_argument("--xci-file", help="XCI file for PS7 configuration")
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parser.add_argument("--target", help="Vivado programmer target")
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builder_args(parser)
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soc_core_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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ext_clk_freq = args.ext_clk_freq,
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xci_file = args.xci_file,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(**vivado_build_argdict(args), run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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bitstream = os.path.join(builder.gateware_dir, soc.build_name + soc.platform.bitstream_ext)
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prog.load_bitstream(bitstream, target=args.target, device=1)
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if __name__ == "__main__":
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main()
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