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qmtech_wukong: review/cleanup platform.

This commit is contained in:
Florent Kermarrec 2020-12-29 14:10:49 +01:00
parent e380f24655
commit b67b18caad
1 changed files with 42 additions and 60 deletions
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102
litex_boards/platforms/qmtech_wukong.py
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@ -13,14 +13,14 @@ from litex.build.openocd import OpenOCD
_io = [ _io = [
# Clk / Rst # Clk / Rst
("clk50", 0, Pins("M22"), IOStandard("LVCMOS33")), ("clk50", 0, Pins("M22"), IOStandard("LVCMOS33")),
("sys_reset", 0, Pins("J8"), IOStandard("LVCMOS33")), ("cpu_reset", 0, Pins("J8"), IOStandard("LVCMOS33")),
# Leds # Leds
("user_led", 0, Pins("J6"), IOStandard("LVCMOS33")), ("user_led", 0, Pins("J6"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("H6"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("H6"), IOStandard("LVCMOS33")),
# Buttons # Buttons
("key0", 0, Pins("H7"), IOStandard("LVCMOS33")), ("user_btn", 0, Pins("H7"), IOStandard("LVCMOS33")), # Key0
# Serial # Serial
("serial", 0, ("serial", 0,
@ -42,7 +42,7 @@ _io = [
("spiflash4x", 0, ("spiflash4x", 0,
Subsignal("cs_n", Pins("P18")), Subsignal("cs_n", Pins("P18")),
Subsignal("clk", Pins("H13")), Subsignal("clk", Pins("H13")),
Subsignal("dq", Pins("R14", "R15", "P14", "N14")), Subsignal("dq", Pins("R14 R15 P14 N14")),
IOStandard("LVCMOS33") IOStandard("LVCMOS33")
), ),
@ -53,10 +53,10 @@ _io = [
"H14 F15 F20 H15 C18 G15"), "H14 F15 F20 H15 C18 G15"),
IOStandard("SSTL135")), IOStandard("SSTL135")),
Subsignal("ba", Pins("B17 D18 A17"), IOStandard("SSTL135")), Subsignal("ba", Pins("B17 D18 A17"), IOStandard("SSTL135")),
Subsignal("ras_n", Pins("A19"), IOStandard("SSTL135")), Subsignal("ras_n", Pins("A19"), IOStandard("SSTL135")),
Subsignal("cas_n", Pins("B19"), IOStandard("SSTL135")), Subsignal("cas_n", Pins("B19"), IOStandard("SSTL135")),
Subsignal("we_n", Pins("A18"), IOStandard("SSTL135")), Subsignal("we_n", Pins("A18"), IOStandard("SSTL135")),
Subsignal("cs_n", Pins("E22"), IOStandard("SSTL135")), Subsignal("cs_n", Pins("E22"), IOStandard("SSTL135")),
Subsignal("dm", Pins("A22 C22"), IOStandard("SSTL135")), Subsignal("dm", Pins("A22 C22"), IOStandard("SSTL135")),
Subsignal("dq", Pins( Subsignal("dq", Pins(
"D21 C21 B22 B21 D19 E20 C19 D20", "D21 C21 B22 B21 D19 E20 C19 D20",
@ -80,13 +80,12 @@ _io = [
# MII Ethernet # MII Ethernet
("eth_ref_clk", 0, Pins("U1"), IOStandard("LVCMOS33")), ("eth_ref_clk", 0, Pins("U1"), IOStandard("LVCMOS33")),
("eth_clocks", 0, ("eth_clocks", 0,
Subsignal("tx", Pins("M2")), Subsignal("tx", Pins("M2")),
Subsignal("rx", Pins("P4")), Subsignal("rx", Pins("P4")),
IOStandard("LVCMOS33") IOStandard("LVCMOS33")
), ),
("eth", 0, ("eth", 0,
Subsignal("rst_n", Pins("R1")), #Signal to ground Subsignal("rst_n", Pins("R1")),
#Subsignal("int_n", Pins("L16")), #Signal to 3.3V
Subsignal("mdio", Pins("H1")), Subsignal("mdio", Pins("H1")),
Subsignal("mdc", Pins("H2")), Subsignal("mdc", Pins("H2")),
Subsignal("rx_dv", Pins("L3")), Subsignal("rx_dv", Pins("L3")),
@ -95,7 +94,7 @@ _io = [
Subsignal("tx_en", Pins("T2")), Subsignal("tx_en", Pins("T2")),
Subsignal("tx_er", Pins("J1")), Subsignal("tx_er", Pins("J1")),
Subsignal("tx_data", Pins("R2 P1 N2 N1 M1 L2 K2 K1")), Subsignal("tx_data", Pins("R2 P1 N2 N1 M1 L2 K2 K1")),
Subsignal("col", Pins("U4")), # col/mod:0 Subsignal("col", Pins("U4")),
Subsignal("crs", Pins("U2")), Subsignal("crs", Pins("U2")),
IOStandard("LVCMOS33") IOStandard("LVCMOS33")
), ),
@ -120,63 +119,44 @@ _io = [
# Connectors --------------------------------------------------------------------------------------- # Connectors ---------------------------------------------------------------------------------------
_connectors = [ _connectors = [
("pmoda", "H4 F4 A4 A5 J4 G4 B4 B5"), ("j10", "H4 F4 A4 A5 J4 G4 B4 B5"),
("pmodb", "D5 G5 G7 G8 E5 E6 D6 G6"), ("j11", "D5 G5 G7 G8 E5 E6 D6 G6"),
# ("j10", "D5 E5 G5 E6 G7 D6 G8 G6"), ("j12", "AB26 AC26 AB24 AC24 AA24 AB25 AA22 AA23",
# ("j11", "J4 G4 B4 B5"), " Y25 AA25 W25 Y26 Y22 Y23 W21 Y21",
("j12", "AB26 AC26 AB24 AC24 AA24 AB25 AA22 AA23 Y25 AA25 W25 Y26 Y22 Y23 W21 Y21 V26 W26 U25 U26 V24 W24 V23 W23 V18 W18 U22 V22 U21 V21 T20 U20 T19 U19"), " V26 W26 U25 U26 V24 W24 V23 W23",
("jp2", "H21 H22 K21 J21 H26 G26 G25 F25 G20 G21 F23 E23 E26 D26 E25 D25"), " V18 W18 U22 V22 U21 V21 T20 U20",
("jp3", "AF7 AE7 AD8 AC8 AF9 AE9 AD12 AC10 AA11 AB11 AF11 AE11 AD14 AC14 AF13 AE13 AD12 AC12"), " T19 U19"),
("jp2", "H21 H22 K21 J21 H26 G26 G25 F25",
"G20 G21 F23 E23 E26 D26 E25 D25"),
("jp3", " AF7 AE7 AD8 AC8 AF9 AE9 AD12 AC10",
"AA11 AB11 AF11 AE11 AD14 AC14 AF13 AE13",
"AD12 AC12"),
] ]
# PMODS -------------------------------------------------------------------------------------------- # PMODS --------------------------------------------------------------------------------------------
'''
#SPI SD CARD
("spisdcard", 0,
Subsignal("clk", Pins("A4")),
Subsignal("cs_n", Pins("A5"), Misc("PULLUP True")),
Subsignal("mosi", Pins("H4"), Misc("PULLUP True")),
Subsignal("miso", Pins("F4"), Misc("PULLUP True")),
IOStandard("LVCMOS33")
),
'''
def sdcard_pmod_io(pmod): def sdcard_pmod_io(pmod):
return [ return [
# SDCard PMOD: # SDCard PMOD:
# - https://store.digilentinc.com/pmod-microsd-microsd-card-slot/ # - https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
# Over J11 connector
# SIGNAL - CONN/PIN
# 3.3V - 6/3.3V
# GND - 5/GND
# MISO - 1/H4
# MOSI - 2/F4
# CLK - 3/A4
# CS - 4/A5
("spisdcard", 0, ("spisdcard", 0,
Subsignal("clk", Pins("A4")), Subsignal("clk", Pins(f"{pmod}:3")),
Subsignal("mosi", Pins("F4"), Misc("PULLUP True")), Subsignal("mosi", Pins(f"{pmod}:1"), Misc("PULLUP True")),
Subsignal("cs_n", Pins("A5"), Misc("PULLUP True")), Subsignal("cs_n", Pins(f"{pmod}:0"), Misc("PULLUP True")),
Subsignal("miso", Pins("H4"), Misc("PULLUP True")), Subsignal("miso", Pins(f"{pmod}:2"), Misc("PULLUP True")),
Misc("SLEW=FAST"), Misc("SLEW=FAST"),
IOStandard("LVCMOS33") IOStandard("LVCMOS33"),
),
("sdcard", 0,
Subsignal("data", Pins(f"{pmod}:2 {pmod}:4 {pmod}:5 {pmod}:0"), Misc("PULLUP True")),
Subsignal("cmd", Pins(f"{pmod}:1"), Misc("PULLUP True")),
Subsignal("clk", Pins(f"{pmod}:3")),
Subsignal("cd", Pins(f"{pmod}:6")),
Misc("SLEW=FAST"),
IOStandard("LVCMOS33"),
), ),
] ]
_sdcard_pmod_io = sdcard_pmod_io("j10") # SDCARD PMOD on J10.
_sdcard_pmod_io = sdcard_pmod_io("pmoda") # SDCARD PMOD on J11.
serial_pmods = [
("serial_pmod0", 0,
Subsignal("rx", Pins("J4"), IOStandard("LVCMOS33")),
Subsignal("tx", Pins("G4"), IOStandard("LVCMOS33")),
),
("serial_pmod1", 0,
Subsignal("rx", Pins("B4"), IOStandard("LVCMOS33")),
Subsignal("tx", Pins("B5"), IOStandard("LVCMOS33")),
),
]
# Platform ----------------------------------------------------------------------------------------- # Platform -----------------------------------------------------------------------------------------
@ -186,11 +166,13 @@ class Platform(XilinxPlatform):
def __init__(self): def __init__(self):
XilinxPlatform.__init__(self, "xc7a100t-2fgg676", _io, _connectors, toolchain="vivado") XilinxPlatform.__init__(self, "xc7a100t-2fgg676", _io, _connectors, toolchain="vivado")
self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] self.toolchain.bitstream_commands = \
self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 16]") self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 16]")
self.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk50_IBUF]") self.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk50_IBUF]")
self.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks UCIO-1]")
def create_programmer(self): def create_programmer(self):
return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a100t.bit") return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a100t.bit")