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Merge pull request #250 from david-sawatzke/fullmemwe 

colorlight_5a_75x: Disable full_memory_we for l2 cache by default
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enjoy-digital 2021-08-11 09:53:47 +02:00 committed by GitHub
parent 615b97e205 9f5e8d4864
commit b77b1514ce
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1 changed files with 5 additions and 3 deletions
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litex_boards/targets/colorlight_5a_75x.py
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@ -152,9 +152,11 @@ class BaseSoC(SoCCore):
else:
sdram_cls = M12L16161A
self.add_sdram("sdram",
phy = self.sdrphy,
module = sdram_cls(sys_clk_freq, sdram_rate),
l2_cache_size = kwargs.get("l2_size", 8192)
phy = self.sdrphy,
module = sdram_cls(sys_clk_freq, sdram_rate),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_full_memory_we = False,
)
# Ethernet / Etherbone ---------------------------------------------------------------------