Merge pull request #250 from david-sawatzke/fullmemwe

colorlight_5a_75x: Disable full_memory_we for l2 cache by default
2021-08-11 09:53:47 +02:00 · 2021-08-11 09:53:47 +02:00 · b77b1514ce
parent 615b97e205 9f5e8d4864
commit b77b1514ce
1 changed files with 5 additions and 3 deletions
--- a/litex_boards/targets/colorlight_5a_75x.py
+++ b/litex_boards/targets/colorlight_5a_75x.py
@ -154,7 +154,9 @@ class BaseSoC(SoCCore):
            self.add_sdram("sdram",
                phy                     = self.sdrphy,
                module                  = sdram_cls(sys_clk_freq, sdram_rate),
-                l2_cache_size = kwargs.get("l2_size", 8192)
+                l2_cache_size           = kwargs.get("l2_size", 8192),
+                l2_cache_full_memory_we = False,
+
            )

        # Ethernet / Etherbone ---------------------------------------------------------------------