targets/sqrl_acorn: write_latency_calibration now disabled by default, no longer required.
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@ -90,8 +90,7 @@ class BaseSoC(SoCCore):
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memtype = "DDR3",
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memtype = "DDR3",
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nphases = 4,
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nphases = 4,
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sys_clk_freq = sys_clk_freq,
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sys_clk_freq = sys_clk_freq,
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iodelay_clk_freq = 200e6,
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iodelay_clk_freq = 200e6)
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write_latency_calibration = False)
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self.add_sdram("sdram",
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self.add_sdram("sdram",
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phy = self.ddrphy,
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phy = self.ddrphy,
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module = MT41K512M16(sys_clk_freq, "1:4"),
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module = MT41K512M16(sys_clk_freq, "1:4"),
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