Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

targets/sqrl_acorn: write_latency_calibration now disabled by default, no longer required.

This commit is contained in:
Florent Kermarrec 2022-03-03 15:50:53 +01:00
parent 26a7f13a7f
commit b80c7a7843
1 changed files with 4 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
litex_boards/targets/sqrl_acorn.py
View File

@ -87,11 +87,10 @@ class BaseSoC(SoCCore):
# DDR3 SDRAM ------------------------------------------------------------------------------- # DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype = "DDR3", memtype = "DDR3",
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 200e6, iodelay_clk_freq = 200e6)
write_latency_calibration = False)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT41K512M16(sys_clk_freq, "1:4"), module = MT41K512M16(sys_clk_freq, "1:4"),