Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

targets/kc705: use DDRPHY_CMD_DELAY to center write leveling.

This commit is contained in:
Florent Kermarrec 2020-02-27 12:58:39 +01:00
parent edcc2cf63e
commit b89af28a05
1 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
litex_boards/targets/kc705.py
View File

@ -57,8 +57,10 @@ class BaseSoC(SoCSDRAM):
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
memtype = "DDR3", memtype = "DDR3",
nphases = 4, nphases = 4,
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq,
cmd_latency = 1)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_constant("DDRPHY_CMD_DELAY", 13)
sdram_module = MT8JTF12864(sys_clk_freq, "1:4") sdram_module = MT8JTF12864(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy, self.register_sdram(self.ddrphy,
geom_settings = sdram_module.geom_settings, geom_settings = sdram_module.geom_settings,