targets/digilent_arty: Add arguments for XDAC and DNA.
Avoid specific checks for Vivado toolchain (Now handled by user for f4pga toolchain) and fix linux-on-litex-vexriscv build.
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@ -71,6 +71,8 @@ class _CRG(LiteXModule):
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class BaseSoC(SoCCore):
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def __init__(self, variant="a7-35", toolchain="vivado", sys_clk_freq=100e6,
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with_xadc = False,
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with_dna = False,
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with_ethernet = False,
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with_etherbone = False,
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eth_ip = "192.168.1.50",
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@ -91,11 +93,11 @@ class BaseSoC(SoCCore):
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Arty A7", **kwargs)
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# XADC -------------------------------------------------------------------------------------
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if toolchain == "vivado":
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if with_xadc:
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self.xadc = XADC()
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# DNA --------------------------------------------------------------------------------------
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if toolchain == "vivado":
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if with_dna:
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self.dna = DNA()
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self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
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@ -161,6 +163,8 @@ def main():
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parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.")
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parser.add_target_argument("--variant", default="a7-35", help="Board variant (a7-35 or a7-100).")
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parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-xadc", action="store_true", help="Enable 7-Series XADC.")
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parser.add_target_argument("--with-dna", action="store_true", help="Enable 7-Series DNA.")
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ethopts = parser.target_group.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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@ -181,6 +185,8 @@ def main():
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variant = args.variant,
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toolchain = args.toolchain,
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sys_clk_freq = args.sys_clk_freq,
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with_xadc = args.with_xadc,
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with_dna = args.with_dna,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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