colorlight_i9plus: Cosmetic cleanups.
This commit is contained in:
Florent Kermarrec
parent
3471617878
commit
b92c96b3a4
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@ -11,11 +11,14 @@ from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk.
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("clk25", 0, Pins("K4"), IOStandard("LVCMOS33")),
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# Leds.
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("user_led", 0, Pins("A18"), IOStandard("LVCMOS33")),
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# RGMII Ethernet (B50612D)
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("eth_clocks", 0, # U5 is SDIO phy #0
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# RGMII Ethernet (B50612D) PHY 0.
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("eth_clocks", 0, # U5 is SDIO phy #0
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Subsignal("tx", Pins("A1")),
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Subsignal("rx", Pins("H4")),
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IOStandard("LVCMOS33")
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@ -30,7 +33,8 @@ _io = [
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Subsignal("tx_data", Pins("B2 B1 C2 D2")),
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IOStandard("LVCMOS33")
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),
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("eth_clocks", 1, # U9 is SDIO phy #1
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# RGMII Ethernet (B50612D) PHY 1.
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("eth_clocks", 1, # U9 is SDIO phy #1
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Subsignal("tx", Pins("M6")),
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Subsignal("rx", Pins("L3")),
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IOStandard("LVCMOS33")
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@ -45,12 +49,12 @@ _io = [
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Subsignal("tx_data", Pins("M5 M2 N4 P4")),
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IOStandard("LVCMOS33")
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),
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# M12L64322A
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# SDRRAM (M12L64322A).
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("sdram_clock", 0, Pins("E14"), IOStandard("LVCMOS33")),
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("sdram", 0,
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Subsignal("a", Pins(
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"C20 C19 C13 F13 G13 G15 "
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"F14 F18 E13 E18 C14 A13")), # address pin A11 routed but NC on M12L64322A
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"F14 F18 E13 E18 C14 A13")), # Address pin A11 routed but NC on M12L64322A
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Subsignal("dq", Pins(
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"F21 E22 F20 E21 F19 D22 E19 D21 "
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"K21 L21 K22 M21 L20 M22 N20 M20 "
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@ -60,10 +64,10 @@ _io = [
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Subsignal("we_n", Pins("D17")),
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Subsignal("ras_n", Pins("A14")),
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Subsignal("cas_n", Pins("D14")),
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#Subsignal("cs_n", Pins("")), # gnd
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#Subsignal("cke", Pins("")), # 3v3
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#Subsignal("cs_n", Pins("")), # GND
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#Subsignal("cke", Pins("")), # 3V3
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Subsignal("ba", Pins("D19 B13")),
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#Subsignal("dm", Pins("")), # gnd
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#Subsignal("dm", Pins("")), # GND
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IOStandard("LVCMOS33"),
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Misc("SLEWRATE=FAST")
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),
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@ -74,30 +78,29 @@ _io = [
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_connectors = [
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("dimm",
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"- "
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"GND 5V GND 5V GND 5V GND 5V GND 5V " # 1-10
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"GND 5V NC NC ETH1_1P ETH2_1P ETH1_1N ETH2_1N NC NC " # 11-20
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"ETH1_2N ETH2_2N ETH1_2P ETH2_2P NC NC ETH1_3P ETH2_3P ETH1_3N ETH2_3N " # 21-30
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"NC NC ETH1_4N ETH2_4N ETH1_4P ETH2_4P NC NC GND GND " # 31-40
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"R2 P5 P6 T6 R6 U7 T1 U6 T3 U5 " # 41-50
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"T4 V5 T4 U1 GND GND U2 H3 U3 J1 " # 51-60
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"V2 K1 V3 L1 W1 M1 Y1 J2 AA1 K2 " # 61-70
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"AB1 K3 W2 G3 Y2 J4 AB2 G4 AA3 F4 " # 71-80
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"AB3 L4 Y3 R3 W4 M3 AA4 V4 Y4 R4 " # 81-90
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"AB5 T5 AA5 J5 Y6 J6 AB6 W5 AA6 L5 " # 91-100
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"Y7 L6 AB7 W6 GND GND GND GND AA8 V7 " # 101-110
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"AB8 N13 Y8 N14 W7 P15 Y9 P16 V8 R16 " # 111-120
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"W9 N17 V9 V17 R14 P17 P14 U17 W17 T18 " # 121-130
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"Y18 R17 AA18 U18 W19 R18 AB18 N18 Y19 R19 " # 131-140
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"AA19 N19 V18 N15 V19 M16 AB20 M15 AA20 L15 " # 141-150
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"AA21 L16 AB21 K14 Y21 N22 GND GND AB22 J14 " # 151-160
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"W20 J15 Y22 J19 W21 H13 W22 H14 V20 H17 " # 161-170
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"V22 H15 U21 G18 U20 G17 T20 G16 P19 F16 " # 171-180
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"P20 F15 M18 E17 L19 E16 J17 D16 K18 D15 " # 181-190
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"K19 C18 K16 C17 H18 B20 H19 B17 NC NC" # 191-200
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" GND 5V GND 5V GND 5V GND 5V GND 5V" # 1-10
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" GND 5V NC NC ETH1_1P ETH2_1P ETH1_1N ETH2_1N NC NC" # 11-20
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"ETH1_2N ETH2_2N ETH1_2P ETH2_2P NC NC ETH1_3P ETH2_3P ETH1_3N ETH2_3N" # 21-30
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" NC NC ETH1_4N ETH2_4N ETH1_4P ETH2_4P NC NC GND GND" # 31-40
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" R2 P5 P6 T6 R6 U7 T1 U6 T3 U5" # 41-50
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" T4 V5 T4 U1 GND GND U2 H3 U3 J1" # 51-60
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" V2 K1 V3 L1 W1 M1 Y1 J2 AA1 K2" # 61-70
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" AB1 K3 W2 G3 Y2 J4 AB2 G4 AA3 F4" # 71-80
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" AB3 L4 Y3 R3 W4 M3 AA4 V4 Y4 R4" # 81-90
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" AB5 T5 AA5 J5 Y6 J6 AB6 W5 AA6 L5" # 91-100
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" Y7 L6 AB7 W6 GND GND GND GND AA8 V7" # 101-110
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" AB8 N13 Y8 N14 W7 P15 Y9 P16 V8 R16" # 111-120
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" W9 N17 V9 V17 R14 P17 P14 U17 W17 T18" # 121-130
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" Y18 R17 AA18 U18 W19 R18 AB18 N18 Y19 R19" # 131-140
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" AA19 N19 V18 N15 V19 M16 AB20 M15 AA20 L15" # 141-150
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" AA21 L16 AB21 K14 Y21 N22 GND GND AB22 J14" # 151-160
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" W20 J15 Y22 J19 W21 H13 W22 H14 V20 H17" # 161-170
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" V22 H15 U21 G18 U20 G17 T20 G16 P19 F16" # 171-180
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" P20 F15 M18 E17 L19 E16 J17 D16 K18 D15" # 181-190
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" K19 C18 K16 C17 H18 B20 H19 B17 NC NC" # 191-200
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)
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]
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def pmod_uart(port="P2"):
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if port == "P2":
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return [
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@ -45,9 +45,9 @@ from liteeth.phy.s7rgmii import LiteEthPHYRGMII
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, with_dram=True, with_ethernet=True):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_idelay = ClockDomain()
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_idelay = ClockDomain()
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if with_dram:
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self.cd_sys_ps = ClockDomain()
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@ -150,18 +150,18 @@ class BaseSoC(SoCCore):
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=colorlight_i9plus.Platform, description="LiteX SoC on Arty A7.")
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parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.")
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parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-dna", action="store_true", help="Enable 7-Series DNA.")
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parser.add_target_argument("--with-pmod-uart", action="store_true", help="Enable uart on P2 (top) PMOD")
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parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.")
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parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-dna", action="store_true", help="Enable 7-Series DNA.")
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parser.add_target_argument("--with-pmod-uart", action="store_true", help="Enable uart on P2 (top) PMOD")
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ethopts = parser.target_group.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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parser.add_target_argument("--eth-port", default=0, type=int, help="Ethernet port to use (0/1)")
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parser.add_target_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
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parser.add_target_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
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parser.add_target_argument("--with-jtagbone", action="store_true", help="Enable JTAGbone support.")
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parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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parser.add_target_argument("--eth-port", default=0, type=int, help="Ethernet port to use (0/1)")
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parser.add_target_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
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parser.add_target_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
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parser.add_target_argument("--with-jtagbone", action="store_true", help="Enable JTAGbone support.")
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parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
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args = parser.parse_args()
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assert not (args.with_etherbone and args.eth_dynamic_ip)
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