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targets: cleanup ECP5 CRGs

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This commit is contained in:
Florent Kermarrec 2020-01-09 14:24:18 +01:00
parent 82601ff700
commit babbc676eb
5 changed files with 26 additions and 41 deletions
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8
litex_boards/official/targets/versa_ecp5.py
View file

@ -37,19 +37,19 @@ class _CRG(Module):
self.stop = Signal()
# clk / rst
# Clk / Rst
clk100 = platform.request("clk100")
rst_n = platform.request("rst_n")
platform.add_period_constraint(clk100, 1e9/100e6)
# power on reset
# Power on reset
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += self.cd_por.clk.eq(ClockSignal())
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# pll
# PLL
self.submodules.pll = pll = ECP5PLL()
pll.register_clkin(clk100, 100e6)
pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
@ -66,7 +66,7 @@ class _CRG(Module):
i_RST = self.cd_sys2x.rst,
o_CDIVX = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | ~rst_n),
AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | ~rst_n)
AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | ~rst_n)
]
# BaseSoC ------------------------------------------------------------------------------------------

14
litex_boards/partner/targets/hadbadge.py
View file

@ -31,22 +31,18 @@ class _CRG(Module):
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys_ps.clk.attr.add("keep")
# clk / rst
# Clk / Rst
clk8 = platform.request("clk8")
rst = Signal()
platform.add_period_constraint(clk8, 1e9/8e6)
# pll
# PLL
self.submodules.pll = pll = ECP5PLL()
pll.register_clkin(clk8, 8e6)
pll.create_clkout(self.cd_sys, sys_clk_freq, phase=11)
pll.create_clkout(self.cd_sys, sys_clk_freq, phase=11)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=20)
self.specials += AsyncResetSynchronizer(self.cd_sys, rst)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
# sdram clock
# SDRAM clock
self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
# BaseSoC ------------------------------------------------------------------------------------------

8
litex_boards/partner/targets/orangecrab.py
View file

@ -35,18 +35,18 @@ class _CRG(Module):
self.stop = Signal()
# clk / rst
# Clk / Rst
clk48 = platform.request("clk48")
platform.add_period_constraint(clk48, 1e9/48e6)
# power on reset
# Power on reset
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += self.cd_por.clk.eq(ClockSignal())
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# pll
# PLL
sys2x_clk_ecsout = Signal()
self.submodules.pll = pll = ECP5PLL()
pll.register_clkin(clk48, 48e6)
@ -69,7 +69,7 @@ class _CRG(Module):
i_RST = self.cd_sys2x.rst,
o_CDIVX = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked),
AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
]
# BaseSoC ------------------------------------------------------------------------------------------

17
litex_boards/partner/targets/trellisboard.py
View file

@ -34,27 +34,21 @@ class _CRG(Module):
# # #
self.cd_init.clk.attr.add("keep")
self.cd_por.clk.attr.add("keep")
self.cd_sys.clk.attr.add("keep")
self.cd_sys2x.clk.attr.add("keep")
self.cd_sys2x_i.clk.attr.add("keep")
self.stop = Signal()
# clk / rst
# Clk / Rst
clk12 = platform.request("clk12")
rst = platform.request("user_btn", 0)
platform.add_period_constraint(clk12, 1e9/12e6)
# power on reset
# Power on reset
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += self.cd_por.clk.eq(ClockSignal())
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# pll
# PLL
sys2x_clk_ecsout = Signal()
self.submodules.pll = pll = ECP5PLL()
pll.register_clkin(clk12, 12e6)
@ -77,11 +71,10 @@ class _CRG(Module):
i_RST = self.cd_sys2x.rst,
o_CDIVX = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | rst),
AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | rst)
AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | rst)
]
vtt_en = platform.request("dram_vtt_en")
self.comb += vtt_en.eq(1)
self.comb += platform.request("dram_vtt_en").eq(1)
# BaseSoC ------------------------------------------------------------------------------------------

20
litex_boards/partner/targets/ulx3s.py
View file

@ -28,28 +28,24 @@ class _CRG(Module):
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys_ps.clk.attr.add("keep")
# clk / rst
# Clk / Rst
clk25 = platform.request("clk25")
rst = platform.request("rst")
platform.add_period_constraint(clk25, 40.0)
platform.add_period_constraint(clk25, 1e9/25e6)
# pll
# PLL
self.submodules.pll = pll = ECP5PLL()
self.comb += pll.reset.eq(rst)
pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys, sys_clk_freq, phase=11)
pll.create_clkout(self.cd_sys, sys_clk_freq, phase=11)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=20)
self.specials += AsyncResetSynchronizer(self.cd_sys, rst)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst)
# sdram clock
# SDRAM clock
self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
# Stop ESP32 from resetting FPGA
wifi_gpio0 = platform.request("wifi_gpio0")
self.comb += wifi_gpio0.eq(1)
# Prevent ESP32 from resetting FPGA
self.comb += platform.request("wifi_gpio0").eq(1)
# BaseSoC ------------------------------------------------------------------------------------------