targets/nexys_video: add SATA support.
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@ -86,7 +86,7 @@ class BaseSoC(SoCCore):
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self.add_csr("ethphy")
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self.add_csr("ethphy")
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self.add_ethernet(phy=self.ethphy)
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self.add_ethernet(phy=self.ethphy)
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# SATA (Experimental) ----------------------------------------------------------------------
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# SATA -------------------------------------------------------------------------------------
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if with_sata:
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if with_sata:
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from litex.build.generic_platform import Subsignal, Pins
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from litex.build.generic_platform import Subsignal, Pins
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from litesata.phy import LiteSATAPHY
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from litesata.phy import LiteSATAPHY
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@ -50,7 +50,7 @@ class _CRG(Module):
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# BaseSoC ------------------------------------------------------------------------------------------
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs):
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def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_sata=False, **kwargs):
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platform = nexys_video.Platform()
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platform = nexys_video.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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# SoCCore ----------------------------------------------------------------------------------
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@ -87,6 +87,36 @@ class BaseSoC(SoCCore):
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self.add_csr("ethphy")
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self.add_csr("ethphy")
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self.add_ethernet(phy=self.ethphy)
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self.add_ethernet(phy=self.ethphy)
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# SATA -------------------------------------------------------------------------------------
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if with_sata:
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from litex.build.generic_platform import Subsignal, Pins
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from litesata.phy import LiteSATAPHY
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# IOs
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_sata_io = [
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# AB09-FMCRAID / https://www.dgway.com/AB09-FMCRAID_E.html
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("fmc2sata", 0,
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Subsignal("clk_p", Pins("LPC:GBTCLK0_M2C_P")),
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Subsignal("clk_n", Pins("LPC:GBTCLK0_M2C_N")),
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Subsignal("tx_p", Pins("LPC:DP0_C2M_P")),
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Subsignal("tx_n", Pins("LPC:DP0_C2M_N")),
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Subsignal("rx_p", Pins("LPC:DP0_M2C_P")),
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Subsignal("rx_n", Pins("LPC:DP0_M2C_N"))
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),
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]
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platform.add_extension(_sata_io)
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# PHY
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self.submodules.sata_phy = LiteSATAPHY(platform.device,
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pads = platform.request("fmc2sata"),
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gen = "gen2",
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clk_freq = sys_clk_freq,
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data_width = 16)
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self.add_csr("sata_phy")
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# Core
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self.add_sata(phy=self.sata_phy, mode="read+write")
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# Leds -------------------------------------------------------------------------------------
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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pads = platform.request_all("user_led"),
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@ -101,12 +131,13 @@ def main():
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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builder_args(parser)
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builder_args(parser)
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soc_sdram_args(parser)
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soc_sdram_args(parser)
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parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
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parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
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parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
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parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
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parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
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parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
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parser.add_argument("--with-sata", action="store_true", help="Enable SATA support (over FMCRAID)")
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args = parser.parse_args()
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args = parser.parse_args()
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soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
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soc = BaseSoC(with_ethernet=args.with_ethernet, with_sata=args.with_sata, **soc_sdram_argdict(args))
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assert not (args.with_spi_sdcard and args.with_sdcard)
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assert not (args.with_spi_sdcard and args.with_sdcard)
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if args.with_spi_sdcard:
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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soc.add_spi_sdcard()
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