adding digilent_arty_z7 support
This commit is contained in:
Gwenhael Goavec-Merou
parent
d52859d9ef
commit
bb92bb00a8
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# This file is Copyright (c) 2019 Michael Betz <michibetz@gmail.com>
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# License: BSD
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from litex.build.generic_platform import Pins, IOStandard, Subsignal
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from litex.build.xilinx import XilinxPlatform
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk125", 0, Pins("H16"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("R14"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("P14"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("N16"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("M14"), IOStandard("LVCMOS33")),
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("rgb_led", 0,
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Subsignal("r", Pins("N15")),
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Subsignal("g", Pins("G17")),
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Subsignal("b", Pins("L15")),
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IOStandard("LVCMOS33"),
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),
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("rgb_led", 1,
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Subsignal("r", Pins("M15")),
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Subsignal("g", Pins("L14")),
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Subsignal("b", Pins("G14")),
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IOStandard("LVCMOS33"),
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),
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# Switches
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("user_sw", 0, Pins("M20"), IOStandard("LVCMOS33")),
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("user_sw", 1, Pins("M19"), IOStandard("LVCMOS33")),
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# Buttons
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("user_btn", 0, Pins("D19"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("D20"), IOStandard("LVCMOS33")),
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("user_btn", 2, Pins("L20"), IOStandard("LVCMOS33")),
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("user_btn", 3, Pins("L19"), IOStandard("LVCMOS33")),
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# Serial (ust to make CI pass)
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# Unfortunately the only USB UART is hard-wired to the ARM CPU
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("serial", 0,
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Subsignal("tx", Pins("Y18")),
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Subsignal("rx", Pins("Y19")),
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IOStandard("LVCMOS33"),
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),
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# SPI
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("spi", 0,
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Subsignal("clk", Pins("H15")),
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Subsignal("cs_n", Pins("F16")),
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Subsignal("mosi", Pins("T12")),
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Subsignal("miso", Pins("W15")),
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IOStandard("LVCMOS33"),
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),
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# I2C
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("i2c", 0,
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Subsignal("scl", Pins("P16")),
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Subsignal("sda", Pins("P15")),
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IOStandard("LVCMOS33"),
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),
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# Audio
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("audio", 0,
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Subsignal("pwm", Pins("R18")), # FIXME
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Subsignal("sd", Pins("T17")), # FIXME
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IOStandard("LVCMOS33"),
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),
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# HDMI In
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("hdmi_in", 0,
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Subsignal("clk_p", Pins("H17"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("P19"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("V20"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("W20"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("T20"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("U20"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("N20"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("P20"), IOStandard("TMDS_33")),
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Subsignal("scl", Pins("U14"), IOStandard("LVCMOS33")),
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Subsignal("sda", Pins("U15"), IOStandard("LVCMOS33")),
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Subsignal("hpd_en", Pins("T19"), IOStandard("LVCMOS33")),
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Subsignal("cec", Pins("H17"), IOStandard("LVCMOS33")),
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),
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# HDMI Out
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("hdmi_out", 0,
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Subsignal("clk_p", Pins("L16"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("L17"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("K17"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("K18"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("K19"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("J19"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("J18"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("H18"), IOStandard("TMDS_33")),
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Subsignal("scl", Pins("M17"), IOStandard("LVCMOS33")),
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Subsignal("sda", Pins("M18"), IOStandard("LVCMOS33")),
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Subsignal("cec", Pins("G15"), IOStandard("LVCMOS33")),
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Subsignal("hdp", Pins("R19"), IOStandard("LVCMOS33")),
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),
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# PS7
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("ps7_clk", 0, Pins(1)),
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("ps7_porb", 0, Pins(1)),
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("ps7_srstb", 0, Pins(1)),
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("ps7_mio", 0, Pins(54)),
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("ps7_ddram", 0,
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Subsignal("addr", Pins(15)),
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Subsignal("ba", Pins(3)),
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Subsignal("cas_n", Pins(1)),
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Subsignal("ck_n", Pins(1)),
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Subsignal("ck_p", Pins(1)),
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Subsignal("cke", Pins(1)),
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Subsignal("cs_n", Pins(1)),
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Subsignal("dm", Pins(4)),
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Subsignal("dq", Pins(32)),
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Subsignal("dqs_n", Pins(4)),
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Subsignal("dqs_p", Pins(4)),
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Subsignal("odt", Pins(1)),
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Subsignal("ras_n", Pins(1)),
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Subsignal("reset_n", Pins(1)),
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Subsignal("we_n", Pins(1)),
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Subsignal("vrn", Pins(1)),
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Subsignal("vrp", Pins(1)),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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# access a pin with `pmoda:N`, where N is:
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# N: 0 1 2 3 4 5 6 7
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# Pin: 1 2 3 4 7 8 9 10
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# Bank 13
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("pmoda", "Y18 Y19 Y16 Y17 U18 U19 W18 W19"),
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("pmodb", "W14 Y14 T11 T10 V16 W16 V12 W13"),
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("ck_io", {
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"ck_ioa" : "Y13",
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# Outer Digital Header
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"ck_io0" : "T14",
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"ck_io1" : "U12",
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"ck_io2" : "U13",
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"ck_io3" : "V13",
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"ck_io4" : "V15",
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"ck_io5" : "T15",
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"ck_io6" : "R16",
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"ck_io7" : "U17",
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"ck_io8" : "V17",
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"ck_io9" : "V18",
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"ck_io10" : "T16",
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"ck_io11" : "R17",
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"ck_io12" : "P18",
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"ck_io13" : "N17",
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# Inner Digital Header
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# Only for Arty Z7 20
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"ck_io26" : "U5",
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"ck_io27" : "V5",
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"ck_io28" : "V6",
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"ck_io29" : "U7",
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"ck_io30" : "V7",
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"ck_io31" : "U8",
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"ck_io32" : "V8",
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"ck_io33" : "V10",
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"ck_io34" : "W10",
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"ck_io35" : "W6",
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"ck_io36" : "Y6",
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"ck_io37" : "Y7",
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"ck_io38" : "W8",
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"ck_io39" : "Y8",
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"ck_io40" : "W9",
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"ck_io41" : "Y9",
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# Outer Analog Header as Digital IO
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# Only for Arty Z7 20
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"ck_a0" : "Y11",
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"ck_a1" : "Y12",
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"ck_a2" : "W11",
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"ck_a3" : "V11",
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"ck_a4" : "T5",
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"ck_a5" : "U10",
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# Inner Analog Header as Digital IO
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"ck_a6" : "F19",
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"ck_a7" : "F20",
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"ck_a8" : "C20",
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"ck_a9" : "B20",
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"ck_a10" : "B19",
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"ck_a11" : "A20",
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}),
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("XADC", {
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# Outer Analog Header
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"vaux1_p" : "E17",
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"vaux1_n" : "B18",
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"vaux9_p" : "E18",
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"vaux9_n" : "E19",
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"vaux6_p" : "K14",
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"vaux6_n" : "J14",
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"vaux15_p" : "K16",
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"vaux15_n" : "J16",
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"vaux5_p" : "J20",
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"vaux5_n" : "H20",
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"vaux13_p" : "G19",
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"vaux13_n" : "G20",
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# Inner Analog Header
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"vaux12_p" : "F19",
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"vaux12_n" : "F20",
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"vaux0_p" : "C20",
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"vaux0_n" : "B20",
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"vaux8_p" : "B19",
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"vaux8_n" : "A19",
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})
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk125"
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default_clk_freq = 125e6
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def __init__(self, variant="z7-20"):
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device = {
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"z7-10": "xc7z010clg400-1",
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"z7-20": "xc7z020clg400-1"
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}[variant]
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self.board = {
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"z7-10": "arty_z7_10",
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"z7-20": "arty_z7_20"
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}[variant]
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XilinxPlatform.__init__(self, device, _io, _connectors,
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toolchain="vivado")
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self.default_clk_period = 1e9 / self.default_clk_freq
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def create_programmer(self):
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return OpenFPGALoader(self.board)
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request(self.default_clk_name, loose=True),
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self.default_clk_period)
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@ -0,0 +1,125 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import argparse
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import subprocess
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from migen import *
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from litex_boards.platforms import digilent_arty_z7
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from litex.build import tools
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from litex.build.xilinx import common as xil_common
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.interconnect import axi
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, use_ps7_clk=False):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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if use_ps7_clk:
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self.comb += ClockSignal("sys").eq(ClockSignal("ps7"))
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self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst)
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else:
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request(platform.default_clk_name), platform.default_clk_freq)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# Ignore sys_clk to pll.clkin path created by SoC's rst.
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, variant="z7-20", sys_clk_freq=int(125e6), with_led_chaser=True, **kwargs):
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platform = digilent_arty_z7.Platform(variant)
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if kwargs.get("cpu_type", None) == "zynq7000":
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kwargs['integrated_sram_size'] = 0
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kwargs['with_uart'] = False
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self.mem_map = {
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'csr': 0x4000_0000, # Zynq GP0 default
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}
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Arty Z7",
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ident_version = True,
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**kwargs)
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# Zynq7000 Integration ---------------------------------------------------------------------
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if kwargs.get("cpu_type", None) == "zynq7000":
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preset_name = "arty_z7_20.tcl" if variant == "z7-20" else "arty_z7_10.tcl"
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os.system("wget http://kmf2.trabucayre.com/" + preset_name)
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self.cpu.set_ps7(preset=preset_name)
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# Connect AXI GP0 to the SoC
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wb_gp0 = wishbone.Interface()
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self.submodules += axi.AXI2Wishbone(
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axi = self.cpu.add_axi_gp_master(),
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wishbone = wb_gp0,
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base_address = self.mem_map['csr'])
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self.add_wb_master(wb_gp0)
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use_ps7_clk = True
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else:
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use_ps7_clk = False
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, use_ps7_clk)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Arty Z7")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--variant", default="z7-20", help="Board variant: z7-20 (default) or z7-10")
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parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: %(default)d)")
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builder_args(parser)
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soc_core_args(parser)
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vivado_build_args(parser)
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parser.set_defaults(cpu_type="zynq7000")
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args = parser.parse_args()
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soc = BaseSoC(
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variant = args.variant,
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sys_clk_freq=int(float(args.sys_clk_freq)),
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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print(builder.compile_software)
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builder.build(**vivado_build_argdict(args), run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if __name__ == "__main__":
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main()
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