Added Arty S7 board
As the pin-out is totally different from the A7 board I did put this in a separate class and not as a variant of the Arty board. Used migen Arty S7 board file and Digilent xdc file as reference.
This commit is contained in:
Staf Verhaegen
parent
188d4a45d6
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bbb1ded9f8
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# This file is Copyright (c) 2015 Yann Sionneau <yann.sionneau@gmail.com>
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# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("user_led", 0, Pins("E18"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("F13"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("E13"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("H15"), IOStandard("LVCMOS33")),
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("rgb_led", 0,
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Subsignal("r", Pins("J15")),
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Subsignal("g", Pins("G17")),
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Subsignal("b", Pins("F15")),
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IOStandard("LVCMOS33")
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),
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("rgb_led", 1,
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Subsignal("r", Pins("E15")),
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Subsignal("g", Pins("F18")),
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Subsignal("b", Pins("E14")),
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IOStandard("LVCMOS33")
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),
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("user_sw", 0, Pins("H14"), IOStandard("LVCMOS33")),
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("user_sw", 1, Pins("H18"), IOStandard("LVCMOS33")),
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("user_sw", 2, Pins("G18"), IOStandard("LVCMOS33")),
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("user_sw", 3, Pins("M5"), IOStandard("SSTL135")),
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("user_btn", 0, Pins("G15"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("K16"), IOStandard("LVCMOS33")),
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("user_btn", 2, Pins("J16"), IOStandard("LVCMOS33")),
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("user_btn", 3, Pins("H13"), IOStandard("LVCMOS33")),
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("clk100", 0, Pins("R2"), IOStandard("SSTL135")),
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("cpu_reset", 0, Pins("C18"), IOStandard("LVCMOS33")),
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("serial", 0,
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Subsignal("tx", Pins("R12")),
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Subsignal("rx", Pins("V12")),
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IOStandard("LVCMOS33")),
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("spi", 0,
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Subsignal("clk", Pins("G16")),
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Subsignal("cs_n", Pins("H16")),
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Subsignal("mosi", Pins("H17")),
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Subsignal("miso", Pins("K14")),
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IOStandard("LVCMOS33")
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),
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("i2c", 0,
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Subsignal("scl", Pins("J14")),
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Subsignal("sda", Pins("J13")),
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IOStandard("LVCMOS33"),
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),
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("spiflash4x", 0, # clock needs to be accessed through STARTUPE2
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Subsignal("cs_n", Pins("M13")),
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Subsignal("clk", Pins("D11")),
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Subsignal("dq", Pins("K17", "K18", "L14", "M15")),
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IOStandard("LVCMOS33")
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),
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("spiflash", 0, # clock needs to be accessed through STARTUPE2
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Subsignal("cs_n", Pins("M13")),
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Subsignal("clk", Pins("D11")),
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Subsignal("mosi", Pins("K17")),
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Subsignal("miso", Pins("K18")),
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Subsignal("wp", Pins("L14")),
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Subsignal("hold", Pins("M15")),
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IOStandard("LVCMOS33")
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),
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("ddram", 0,
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Subsignal("a", Pins(
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"U2 R4 V2 V4 T3 R7 V6 T6",
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"U7 V7 P6 T5 R6 U6"),
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IOStandard("SSTL135")),
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Subsignal("ba", Pins("V5 T1 U3"), IOStandard("SSTL135")),
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Subsignal("ras_n", Pins("U1"), IOStandard("SSTL135")),
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Subsignal("cas_n", Pins("V3"), IOStandard("SSTL135")),
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Subsignal("we_n", Pins("P7"), IOStandard("SSTL135")),
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Subsignal("cs_n", Pins("R3"), IOStandard("SSTL135")),
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Subsignal("dm", Pins("K4 M3"), IOStandard("SSTL135")),
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Subsignal("dq", Pins(
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"K2 K3 L4 M6 K6 M4 L5 L6",
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"N4 R1 N1 N5 M2 P1 M1 P2"),
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IOStandard("SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_p", Pins("K1 N3"),
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IOStandard("DIFF_SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("dqs_n", Pins("L1 N2"),
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IOStandard("DIFF_SSTL135"),
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Misc("IN_TERM=UNTUNED_SPLIT_40")),
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Subsignal("clk_p", Pins("R5"), IOStandard("DIFF_SSTL135")),
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Subsignal("clk_n", Pins("T4"), IOStandard("DIFF_SSTL135")),
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Subsignal("cke", Pins("T2"), IOStandard("SSTL135")),
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Subsignal("odt", Pins("P5"), IOStandard("SSTL135")),
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Subsignal("reset_n", Pins("J6"), IOStandard("SSTL135")),
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Misc("SLEW=FAST"),
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("pmoda", "L17 L18 M14 N14 M16 M17 M18 N18"),
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("pmodb", "P17 P18 R18 T18 P14 P15 N15 P16"),
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("pmodc", "U15 V16 U17 U18 U16 P13 R13 V14"),
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("pmodd", "V15 U12 V13 T12 T13 R11 T11 U11"),
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("ck_io", {
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# Outer Digital Header
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"ck_io0" : "L13",
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"ck_io1" : "N13",
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"ck_io2" : "L16",
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"ck_io3" : "R14",
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"ck_io4" : "T14",
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"ck_io5" : "R16",
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"ck_io6" : "R17",
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"ck_io7" : "V17",
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"ck_io8" : "R15",
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"ck_io9" : "T15",
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"ck_io10" : "H16",
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"ck_io11" : "H17",
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"ck_io12" : "K14",
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"ck_io13" : "G16",
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# Inner Digital Header
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"ck_io26" : "U11",
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"ck_io27" : "T11",
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"ck_io28" : "R11",
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"ck_io29" : "T13",
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"ck_io30" : "T12",
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"ck_io31" : "V13",
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"ck_io32" : "U12",
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"ck_io33" : "V15",
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"ck_io34" : "V14",
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"ck_io35" : "R13",
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"ck_io36" : "P13",
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"ck_io37" : "U16",
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"ck_io38" : "U18",
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"ck_io39" : "U17",
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"ck_io40" : "V16",
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"ck_io41" : "U15",
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# Outer Analog Header as Digital IO
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"ck_a0" : "G13",
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"ck_a1" : "B16",
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"ck_a2" : "A16",
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"ck_a3" : "C13",
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"ck_a4" : "C14",
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"ck_a5" : "D18",
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# Inner Analog Header as Digital IO
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"ck_a6" : "B14",
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"ck_a7" : "A14",
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"ck_a8" : "D16",
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"ck_a9" : "D17",
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"ck_a10" : "D14",
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"ck_a11" : "D15",
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} ),
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("XADC", {
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# Outer Analog Header
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"vaux0_p" : "B13",
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"vaux0_n" : "A13",
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"vaux1_p" : "B15",
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"vaux1_n" : "A15",
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"vaux9_p" : "E12",
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"vaux9_n" : "D12",
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"vaux2_p" : "B17",
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"vaux2_n" : "A17",
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"vaux10_p" : "C17",
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"vaux10_n" : "B18",
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"vaux11_p" : "E16",
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"vaux11_n" : "E17",
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# Inner Analog Header
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"vaux8_p" : "B14",
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"vaux8_n" : "A14",
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"vaux3_p" : "D16",
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"vaux3_n" : "D17",
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} ),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self, variant="s7-50"):
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device = {
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"s7-25": "xc7s25csga324-1",
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"s7-50": "xc7s50csga324-1"
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}[variant]
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XilinxPlatform.__init__(self, device, _io, _connectors, toolchain="vivado")
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
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def create_programmer(self):
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return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")
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@ -0,0 +1,91 @@
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#!/usr/bin/env python3
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# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>,
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# Copyright (c) 2020 Staf Verhaegen <staf@fibraservi.eu>
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# License: BSD
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import argparse
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from migen import Module, ClockDomain
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from ..platforms import artys7
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.cores.clock import S7PLL, S7IDELAYCTRL
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict
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from litex.soc.integration.builder import Builder, builder_args, builder_argdict
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from litedram.modules import MT41K128M16
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from litedram.phy import s7ddrphy
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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# # #
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(~platform.request("cpu_reset"))
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pll.register_clkin(platform.request("clk100"), 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_clk200, 200e6)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(100e6), **kwargs):
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platform = artys7.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq,
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interface_type = "MEMORY")
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self.add_csr("ddrphy")
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41K128M16(sys_clk_freq, "1:4"),
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origin = self.mem_map["main_ram"],
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size = kwargs.get("max_sdram_size", 0x40000000),
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l2_cache_size = kwargs.get("l2_size", 8192),
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l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
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l2_cache_reverse = True
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)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Arty")
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builder_args(parser)
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soc_sdram_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(with_ethernet=False, with_etherbone=False,
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**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(**vivado_build_argdict(args))
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if __name__ == "__main__":
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main()
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