platforms/xilinx_alveo_u250: Fix dram numbering.

2023-01-16 09:31:23 +01:00 · 2023-01-16 09:31:23 +01:00 · be77f82720
parent e02f64a7db
commit be77f82720
1 changed files with 1 additions and 1 deletions
--- a/litex_boards/platforms/xilinx_alveo_u250.py
+++ b/litex_boards/platforms/xilinx_alveo_u250.py
@ -192,7 +192,7 @@ _io = [
        Subsignal("we_n", Pins("A35"), IOStandard("SSTL12_DCI")),
        Misc("SLEW=FAST")
    ),
-    ("ddram", 4,
+    ("ddram", 3,
        Subsignal("a", Pins(
            "K15 B15 F14 A15 C14 A14 B14 E13",
            "F13 A13 D14 C13 B13 K16"),