Merge pull request #432 from fjullien/add_qmtech_cyclone_4_starter_kit
Add qmtech Cyclone IV Starter Kit
This commit is contained in:
enjoy-digital
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be8cd1f8a4
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Franck Jullien <franck.jullien@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.altera import AlteraPlatform
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from litex.build.altera.programmer import USBBlaster
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk
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("clk50", 0, Pins("T2"), IOStandard("3.3-V LVTTL")),
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# LED
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("led", 0, Pins("E3"), IOStandard("3.3-V LVTTL")),
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# Button
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("key", 0, Pins("J4"), IOStandard("3.3-V LVTTL")),
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("serial", 0,
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Subsignal("tx", Pins("Y22"), IOStandard("3.3-V LVTTL")),
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Subsignal("rx", Pins("Y21"), IOStandard("3.3-V LVTTL"))
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),
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# 7-segments display
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("seven_seg_ctl", 0,
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Subsignal("dig", Pins("Y13 W13 V13")),
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Subsignal("segments", Pins("V15 U20 W20 Y17 W15 W17 U19")),
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Subsignal("dot", Pins("W19")),
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IOStandard("3.3-V LVTTL")
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),
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# VGA
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("vga", 0,
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Subsignal("hsync_n", Pins("AA13")),
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Subsignal("vsync_n", Pins("AB10")),
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Subsignal("r", Pins("AB19 AA19 AB20 AA20 AA21")),
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Subsignal("g", Pins("AB16 AA16 AB17 AA17 AA18 AB18")),
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Subsignal("b", Pins("AA14 AB13 AA15 AB14 AB15")),
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IOStandard("3.3-V LVTTL")
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),
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# SPIFlash (W25Q64)
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("spiflash", 0,
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# clk
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Subsignal("cs_n", Pins("E2")),
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Subsignal("clk", Pins("K2")),
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Subsignal("mosi", Pins("D1")),
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Subsignal("miso", Pins("E2")),
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IOStandard("3.3-V LVTTL"),
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),
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# SDR SDRAM
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("sdram_clock", 0, Pins("Y6"), IOStandard("3.3-V LVTTL")),
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("sdram", 0,
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Subsignal("a", Pins(
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"V2 V1 U2 U1 V3 V4 Y2 AA1",
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"Y3 V5 W1 Y4 V6")),
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Subsignal("ba", Pins("Y1 W2")),
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Subsignal("cs_n", Pins("AA3")),
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Subsignal("cke", Pins("W6")),
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Subsignal("ras_n", Pins("AB3")),
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Subsignal("cas_n", Pins("AA4")),
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Subsignal("we_n", Pins("AB4")),
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Subsignal("dq", Pins(
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"AA10 AB9 AA9 AB8 AA8 AB7 AA7 AB5",
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"Y7 W8 Y8 V9 V10 Y10 W10 V11")),
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Subsignal("dm", Pins("AA5 W7")),
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IOStandard("3.3-V LVTTL")
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),
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# GMII Ethernet
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("eth_clocks", 0,
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Subsignal("tx", Pins("R22")),
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Subsignal("gtx", Pins("L21")),
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Subsignal("rx", Pins("F21")),
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IOStandard("3.3-V LVTTL")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("N22")),
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Subsignal("mdio", Pins("W21")),
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Subsignal("mdc", Pins("W22")),
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Subsignal("rx_dv", Pins("D22")),
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Subsignal("rx_er", Pins("K22")),
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Subsignal("rx_data", Pins("D21 E22 E21 F22 H22 H21 J22 J21")),
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Subsignal("tx_en", Pins("M22")),
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Subsignal("tx_er", Pins("V21")),
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Subsignal("tx_data", Pins("M21 N21 P22 P21 R21 U22 U21 V22")),
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Subsignal("col", Pins("K21")),
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Subsignal("crs", Pins("L22")),
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IOStandard("3.3-V LVTTL")
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),
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]
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_connectors = [
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("J11", {
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1: "R1", 7: "R2",
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2: "P1", 8: "P2",
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3: "N1", 9: "N2",
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4: "M1", 10: "M2",
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5: "-" , 11: "-",
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6: "-" , 12: "-",
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}),
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("J10", {
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1: "J1", 7: "J2",
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2: "H1", 8: "H2",
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3: "F1", 9: "F2",
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4: "E1", 10: "D2",
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5: "-" , 11: "-",
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6: "-" , 12: "-",
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}),
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("JP1", {
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1: "-", 2: "-",
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3: "A8", 4: "B8",
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5: "A7", 6: "B7",
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7: "A6", 8: "B6",
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9: "A5", 10: "B5",
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11: "A4", 12: "B4",
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13: "A3", 14: "B3",
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15: "B1", 16: "B2",
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17: "C1", 18: "C2",
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}),
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("J12", {
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1: "-", 2: "-",
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3: "C22", 4: "C21",
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5: "B22", 6: "B21",
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7: "H20", 8: "H19",
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9: "F20", 10: "F19",
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11: "C20", 12: "D20",
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13: "C19", 14: "D19",
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15: "C17", 16: "D17",
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17: "A20", 18: "B20",
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19: "A19", 20: "B19",
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21: "A18", 22: "B18",
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23: "A17", 24: "B17",
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25: "A16", 26: "B16",
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27: "A15", 28: "B15",
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29: "A14", 30: "B14",
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31: "A13", 32: "B13",
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33: "A10", 34: "B10",
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35: "A9", 36: "B9",
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37: "-", 38: "-",
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39: "-", 40: "-",
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})
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(AlteraPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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def __init__(self, toolchain="quartus"):
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AlteraPlatform.__init__(self, "EP4CE15F23C8", _io, _connectors, toolchain=toolchain)
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self.add_platform_command("set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
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def create_programmer(self):
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return USBBlaster()
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def do_finalize(self, fragment):
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AlteraPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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@ -0,0 +1,135 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Franck Jullien <franck.jullien@collshade.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.io import DDROutput
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from litex_boards.platforms import qmtech_ep4ce15_starter_kit
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from litex.soc.cores.clock import CycloneIVPLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import W9825G6KH6
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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if sdram_rate == "1:2":
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_ps = ClockDomain()
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else:
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self.clock_domains.cd_sys_ps = ClockDomain()
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# # #
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# Clk / Rst
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clk50 = platform.request("clk50")
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# PLL
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self.submodules.pll = pll = CycloneIVPLL(speedgrade="-6")
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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if sdram_rate == "1:2":
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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# theoretically 90 degrees, but increase to relax timing
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pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180)
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else:
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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# SDRAM clock
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sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), with_jtaguart=False, with_jtagbone=False,
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with_led_chaser=True, sdram_rate="1:1", **kwargs):
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platform = qmtech_ep4ce15_starter_kit.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate = sdram_rate)
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# SoCCore ----------------------------------------------------------------------------------
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if with_jtagbone:
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kwargs["uart_name"] = "crossover"
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if with_jtaguart:
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kwargs["uart_name"] = "jtag_uart"
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on QMTECH Cyclone IV Starter Kit",
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**kwargs
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)
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# JTAGbone ---------------------------------------------------------------------------------
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if with_jtagbone:
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self.add_jtagbone()
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
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self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = W9825G6KH6(sys_clk_freq, sdram_rate),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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seven_seg_display = platform.request("seven_seg_ctl")
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self.comb += seven_seg_display.dig.eq(0b111)
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self.submodules.leds = LedChaser(
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pads = seven_seg_display.segments,
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on QMTECH EP4CE15")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build design.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
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target_group.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
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target_group.add_argument("--with-jtaguart", action="store_true", help="Enable JTAGUart support.")
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target_group.add_argument("--with-jtagbone", action="store_true", help="Enable JTAGbone support.")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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sdram_rate = args.sdram_rate,
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with_jtagbone = args.with_jtagbone,
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with_jtaguart = args.with_jtaguart,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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if args.build:
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builder.build()
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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