orangecrab: reduce DDR3 power consumption/heat and get back USB PLL to CRGSDRAM.

- disable DQ termination.
- disable RTT_NOM.
- drive VCCIO/GND pads.

Reduce current from 0.25A to 0.12A with: ./orangecrab.py --uart-name=usb_acm --sys-clk-freq=48e6.
Still working at 96MHz, 0.17A with: ./orangecrab.py --uart-name=usb_acm --sys-clk-freq=96e6.

See https://github.com/enjoy-digital/litedram/issues/216.
This commit is contained in:
Florent Kermarrec 2020-08-28 20:01:54 +02:00
parent 63b65e278c
commit beccecf59f
2 changed files with 20 additions and 3 deletions

View File

@ -113,7 +113,7 @@ _io_r0_2 = [
"C17 D15 B17 C16 A15 B13 A17 A13",
"F17 F16 G15 F15 J16 C18 H16 F18"),
IOStandard("SSTL135_I"),
Misc("TERMINATION=75")),
Misc("TERMINATION=OFF")), # Misc("TERMINATION=75") Disabled to reduce heat
Subsignal("dqs_p", Pins("B15 G18"), IOStandard("SSTL135D_I"),
Misc("TERMINATION=OFF"),
Misc("DIFFRESISTOR=100")),

View File

@ -74,6 +74,7 @@ class _CRGSDRAM(Module):
# # #
self.stop = Signal()
self.reset = Signal()
@ -114,6 +115,16 @@ class _CRGSDRAM(Module):
AsyncResetSynchronizer(self.cd_sys2x, ~por_done | ~pll.locked | ~rst_n | self.reset),
]
# USB PLL
if with_usb_pll:
self.clock_domains.cd_usb_12 = ClockDomain()
self.clock_domains.cd_usb_48 = ClockDomain()
usb_pll = ECP5PLL()
self.submodules += usb_pll
usb_pll.register_clkin(clk48, 48e6)
usb_pll.create_clkout(self.cd_usb_48, 48e6)
usb_pll.create_clkout(self.cd_usb_12, 12e6)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
@ -150,10 +161,16 @@ class BaseSoC(SoCCore):
}
sdram_module = available_sdram_modules.get(sdram_device)
ddram_pads = platform.request("ddram")
self.submodules.ddrphy = ECP5DDRPHY(
platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
pads = ddram_pads,
sys_clk_freq = sys_clk_freq)
self.ddrphy.settings.rtt_nom = "disabled"
self.add_csr("ddrphy")
if hasattr(ddram_pads, "vccio"):
self.comb += ddram_pads.vccio.eq(0b111111)
if hasattr(ddram_pads, "gnd"):
self.comb += ddram_pads.gnd.eq(0)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram",