orangecrab: reduce DDR3 power consumption/heat and get back USB PLL to CRGSDRAM.
- disable DQ termination. - disable RTT_NOM. - drive VCCIO/GND pads. Reduce current from 0.25A to 0.12A with: ./orangecrab.py --uart-name=usb_acm --sys-clk-freq=48e6. Still working at 96MHz, 0.17A with: ./orangecrab.py --uart-name=usb_acm --sys-clk-freq=96e6. See https://github.com/enjoy-digital/litedram/issues/216.
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@ -113,7 +113,7 @@ _io_r0_2 = [
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"C17 D15 B17 C16 A15 B13 A17 A13",
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"F17 F16 G15 F15 J16 C18 H16 F18"),
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IOStandard("SSTL135_I"),
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Misc("TERMINATION=75")),
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Misc("TERMINATION=OFF")), # Misc("TERMINATION=75") Disabled to reduce heat
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Subsignal("dqs_p", Pins("B15 G18"), IOStandard("SSTL135D_I"),
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Misc("TERMINATION=OFF"),
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Misc("DIFFRESISTOR=100")),
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@ -74,6 +74,7 @@ class _CRGSDRAM(Module):
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# # #
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self.stop = Signal()
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self.reset = Signal()
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@ -114,6 +115,16 @@ class _CRGSDRAM(Module):
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AsyncResetSynchronizer(self.cd_sys2x, ~por_done | ~pll.locked | ~rst_n | self.reset),
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]
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# USB PLL
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if with_usb_pll:
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self.clock_domains.cd_usb_12 = ClockDomain()
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self.clock_domains.cd_usb_48 = ClockDomain()
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usb_pll = ECP5PLL()
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self.submodules += usb_pll
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usb_pll.register_clkin(clk48, 48e6)
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usb_pll.create_clkout(self.cd_usb_48, 48e6)
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usb_pll.create_clkout(self.cd_usb_12, 12e6)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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@ -150,10 +161,16 @@ class BaseSoC(SoCCore):
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}
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sdram_module = available_sdram_modules.get(sdram_device)
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ddram_pads = platform.request("ddram")
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self.submodules.ddrphy = ECP5DDRPHY(
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platform.request("ddram"),
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sys_clk_freq=sys_clk_freq)
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pads = ddram_pads,
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sys_clk_freq = sys_clk_freq)
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self.ddrphy.settings.rtt_nom = "disabled"
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self.add_csr("ddrphy")
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if hasattr(ddram_pads, "vccio"):
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self.comb += ddram_pads.vccio.eq(0b111111)
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if hasattr(ddram_pads, "gnd"):
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self.comb += ddram_pads.gnd.eq(0)
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self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
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self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
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self.add_sdram("sdram",
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