targets/hadbadge: cleanup/simplify (keep things similar to ulx3s) and add copyrights
This commit is contained in:
Florent Kermarrec
parent
85c4f76eba
commit
c0e4578bea
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@ -1,7 +1,9 @@
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#!/usr/bin/env python3
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#!/usr/bin/env python3
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# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2020 Michael Welling <mwelling@ieee.org>
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# This file is Copyright (c) 2018 David Shah <dave@ds0.me>
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# This file is Copyright (c) 2020 Sean Cross <sean@xobs.io>
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# This file is Copyright (c) 2020 Drew Fustini <drew@pdp7.com>
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# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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# License: BSD
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import argparse
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import argparse
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@ -14,205 +16,61 @@ from litex_boards.platforms import hadbadge
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from litex.soc.cores.clock import *
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.soc_sdram import *
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#from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.integration.builder import *
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#from .spi_ram_dual import SpiRamDualQuad
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from litedram import modules as litedram_modules
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from litedram import modules as litedram_modules
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from litedram.phy import GENSDRPHY
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from litedram.phy import GENSDRPHY
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from litedram.modules import AS4C32M8
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# CRG ----------------------------------------------------------------------------------------------
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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class _CRG(Module):
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"""Clock Resource Generator"
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Input: 8 MHz
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Output: 48 MHz
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"""
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def __init__(self, platform, sys_clk_freq):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_clk12 = ClockDomain()
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self.clock_domains.cd_clk48 = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
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# # #
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# # #
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self.cd_sys.clk.attr.add("keep")
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self.cd_sys.clk.attr.add("keep")
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self.cd_por.clk.attr.add("keep")
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self.cd_clk12.clk.attr.add("keep")
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self.cd_clk48.clk.attr.add("keep")
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self.cd_sys_ps.clk.attr.add("keep")
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self.cd_sys_ps.clk.attr.add("keep")
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self.stop = Signal()
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# clk / rst
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# clk / rst
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clk8 = platform.request("clk8")
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clk8 = platform.request("clk8")
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# rst_n = platform.request("rst_n")
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rst = Signal()
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platform.add_period_constraint(clk8, 1e9/8e6)
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platform.add_period_constraint(clk8, 1e9/8e6)
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platform.add_period_constraint(self.cd_sys.clk, 1e9/48e6)
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platform.add_period_constraint(self.cd_clk12.clk, 1e9/12e6)
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platform.add_period_constraint(self.cd_clk48.clk, 1e9/48e6)
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# power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(clk8)
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# pll
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# pll
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self.submodules.pll = pll = ECP5PLL()
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self.submodules.pll = pll = ECP5PLL()
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pll.register_clkin(clk8, 8e6)
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pll.register_clkin(clk8, 8e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, phase=0, margin=1e-9)
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pll.create_clkout(self.cd_sys, sys_clk_freq, phase=11)
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pll.create_clkout(self.cd_clk12, 12e6, phase=39, margin=1e-9)
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=20)
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=20)
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self.comb += self.cd_clk48.clk.eq(self.cd_sys.clk)
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self.specials += AsyncResetSynchronizer(self.cd_sys, rst)
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# pll.create_clkout(self.cd_sys, 48e6, phase=0, margin=1e-9)
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# pll.create_clkout(self.cd_clk12, 12e6, phase=132, margin=1e-9)
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# sdram clock
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# sdram clock
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self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
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self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
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# Synchronize USB48 and USB12, and drive USB12 from USB48
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self.specials += [
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# Instance("ECLKSYNCB",
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# i_ECLKI=self.cd_usb48_i.clk,
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# i_STOP=self.stop,
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# o_ECLKO=self.cd_usb48.clk),
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# Instance("CLKDIVF",
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# p_DIV="2.0",
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# i_ALIGNWD=0,
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# i_CLKI=self.cd_usb48.clk,
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# i_RST=self.cd_usb48.rst,
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# o_CDIVX=self.cd_usb12.clk),
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AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked),# | ~rst_n),
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AsyncResetSynchronizer(self.cd_clk12, ~por_done | ~pll.locked),# | ~rst_n),
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# AsyncResetSynchronizer(self.cd_usb48, ~por_done | ~pll.locked),# | ~rst_n)
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]
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# BaseSoC ------------------------------------------------------------------------------------------
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCSDRAM):
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class BaseSoC(SoCSDRAM):
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# SoCCore.csr_map = {
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def __init__(self, toolchain="trellis", sys_clk_freq=int(48e6), sdram_module_cls="AS4C32M8", **kwargs):
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# "ctrl": 0, # provided by default (optional)
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platform = hadbadge.Platform(toolchain=toolchain)
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# "crg": 1, # user
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platform.toolchain.build_template[1] += " --speed 8" # Add "speed grade 8" to nextpnr-ecp5 # FIXME
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# "uart_phy": 2, # provided by default (optional)
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# "uart": 3, # provided by default (optional)
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# "identifier_mem": 4, # provided by default (optional)
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# "timer0": 5, # provided by default (optional)
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# "picorvspi": 7,
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# "lcdif": 8,
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# "usb": 9,
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# "reboot": 12,
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# "rgb": 13,
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# "version": 14,
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# "lxspi": 15,
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# "messible": 16,
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# }
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# We must define memory offsets here rather than using the litex
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# SoCSDRAM ---------------------------------------------------------------------------------
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# defaults. This is because the mmu only allows for certain
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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# regions to be unbuffered:
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integrated_rom_size=0x8000,
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# https://github.com/m-labs/VexRiscv-verilog/blob/master/src/main/scala/vexriscv/GenCoreDefault.scala#L139-L143
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**kwargs)
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SoCSDRAM.mem_map = {
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"rom": 0x00000000,
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"sram": 0x10000000,
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"emulator_ram": 0x20000000,
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"ethmac": 0x30000000,
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"spiflash": 0x50000000,
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"main_ram": 0xc0000000,
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"csr": 0xe0000000,
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}
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def __init__(self, debug=True, sdram_module_cls="AS4C32M8", **kwargs):
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# CRG --------------------------------------------------------------------------------------
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platform = hadbadge.Platform()
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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clk_freq = int(48e6)
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SoCSDRAM.__init__(self, platform, clk_freq,
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integrated_rom_size=16384,
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integrated_sram_size=65536,
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wishbone_timeout_cycles=1e9,
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**kwargs)
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self.submodules.crg = _CRG(self.platform, sys_clk_freq=clk_freq)
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# Add a "Version" module so we can see what version of the board this is.
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# self.submodules.version = Version("proto2", [
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# (0x02, "proto2", "Prototype Version 2 (red)")
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# ], 0)
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# Add a "USB" module to let us debug the device.
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# usb_pads = platform.request("usb")
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# usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
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# self.submodules.usb = ClockDomainsRenamer({
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# "usb_48": "clk48",
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# "usb_12": "clk12",
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# })(DummyUsb(usb_iobuf, debug=debug, product="Hackaday Supercon Badge", cdc=True))
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#
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# if debug:
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# self.add_wb_master(self.usb.debug_bridge.wishbone)
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#
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# if self.cpu_type is not None:
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# self.register_mem("vexriscv_debug", 0xb00f0000, self.cpu.debug_bus, 0x200)
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# self.cpu.use_external_variant("rtl/VexRiscv_HaD_Debug.v")
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# elif self.cpu_type is not None:
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# self.cpu.use_external_variant("rtl/VexRiscv_HaD.v")
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# Add the 16 MB SPI flash as XIP memory at address 0x03000000
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# if not is_sim:
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# # flash = SpiFlashDualQuad(platform.request("spiflash4x"), dummy=5)
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# # flash.add_clk_primitive(self.platform.device)
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# # self.submodules.lxspi = flash
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# # self.register_mem("spiflash", 0x03000000, self.lxspi.bus, size=16 * 1024 * 1024)
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# self.submodules.picorvspi = flash = PicoRVSpi(self.platform, pads=platform.request("spiflash"), size=16 * 1024 * 1024)
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# self.register_mem("spiflash", self.mem_map["spiflash"], self.picorvspi.bus, size=self.picorvspi.size)
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# # Add the 16 MB SPI RAM at address 0x40000000 # Value at 40010000: afbfcfef
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# reset_cycles = 2**14-1
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# ram = SpiRamDualQuad(platform.request("spiram4x", 0), platform.request("spiram4x", 1), dummy=5, reset_cycles=reset_cycles, qpi=True)
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# self.submodules.ram = ram
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# self.register_mem("main_ram", self.mem_map["main_ram"], self.ram.bus, size=16 * 1024 * 1024)
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self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2)
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sdram_module = getattr(litedram_modules, sdram_module_cls)(clk_freq, "1:1")
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self.register_sdram(self.sdrphy,
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sdram_module.geom_settings,
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sdram_module.timing_settings)
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# Let us reboot the device
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# self.submodules.reboot = Reboot(platform.request("programn"))
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# Add a Messible for sending messages to the host
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# self.submodules.messible = Messible()
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# Add an LCD so we can see what's up
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# self.submodules.lcdif = LCDIF(platform.request("lcd"))
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# Ensure timing is correctly set up
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self.platform.toolchain.build_template[1] += " --speed 8" # Add "speed grade 8" to nextpnr-ecp5
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# SAO
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# self.submodules.sao0 = ShittyAddOn(self.platform, self.platform.request("sao", 0), disable_i2c=kwargs["sao0_disable_i2c"]);
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# self.add_csr("sao0")
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# self.submodules.sao1 = ShittyAddOn(self.platform, self.platform.request("sao", 1), disable_i2c=kwargs["sao1_disable_i2c"]);
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# self.add_csr("sao1")
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# # PMOD
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# platform.add_extension(_pmod_gpio)
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# self.submodules.pmod = GPIOBidirectional(self.platform.request("pmod_gpio"))
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# self.add_csr("pmod")
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# # GENIO
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# platform.add_extension(_genio_gpio)
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# self.submodules.genio = GPIOBidirectional(self.platform.request("genio_gpio"))
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# self.add_csr("genio")
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# # LEDs
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# self.submodules.led0 = gpio.GPIOOut(self.platform.request("led", 0))
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# self.add_csr("led0")
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# self.submodules.led1 = gpio.GPIOOut(self.platform.request("led", 1))
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# self.add_csr("led1")
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# # Keypad
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# self.submodules.keypad = gpio.GPIOIn(Cat(self.platform.request("keypad", 0).flatten()))
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# self.add_csr("keypad")
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2)
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sdram_module = AS4C32M8(sys_clk_freq, "1:1")
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self.register_sdram(self.sdrphy,
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sdram_module.geom_settings,
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sdram_module.timing_settings)
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# Build --------------------------------------------------------------------------------------------
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# Build --------------------------------------------------------------------------------------------
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@ -220,25 +78,15 @@ def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Hackaday Badge")
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parser = argparse.ArgumentParser(description="LiteX SoC on Hackaday Badge")
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parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis",
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parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis",
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help='gateware toolchain to use, diamond or trellis (default)')
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help='gateware toolchain to use, diamond or trellis (default)')
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parser.add_argument("--device", dest="device", default="LFE5U-45F",
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help='FPGA device, Hackaday badge is populated with LFE5U-45F')
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parser.add_argument("--sys-clk-freq", default=48e6,
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parser.add_argument("--sys-clk-freq", default=48e6,
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help="system clock frequency (default=48MHz)")
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help="system clock frequency (default=48MHz)")
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parser.add_argument("--sdram-module", default="MT48LC16M16",
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help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)")
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builder_args(parser)
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builder_args(parser)
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soc_sdram_args(parser)
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soc_sdram_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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args = parser.parse_args()
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# soc = BaseSoC(device=args.device,
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soc = BaseSoC(toolchain=args.toolchain,
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# sys_clk_freq=int(float(args.sys_clk_freq)),
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# **soc_core_argdict(args))
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soc = BaseSoC(device=args.device, toolchain=args.toolchain,
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sys_clk_freq=int(float(args.sys_clk_freq)),
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sys_clk_freq=int(float(args.sys_clk_freq)),
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sdram_module_cls=args.sdram_module,
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**soc_sdram_argdict(args))
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**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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builder.build()
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