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analog_pocket: Add Serial (to fix CI) and add to board list.

This commit is contained in:
Florent Kermarrec 2023-09-21 10:11:47 +02:00
parent 3df677cfeb
commit c14d66cb6b
2 changed files with 8 additions and 0 deletions
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1
README.md
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@ -99,6 +99,7 @@ Some of the suported boards, see yours? Give LiteX-Boards a try!
├── aliexpress_xc7k420t ├── aliexpress_xc7k420t
├── alinx_ax7010 ├── alinx_ax7010
├── alinx_axu2cga ├── alinx_axu2cga
├── analog_pocket
├── antmicro_artix_dc_scm ├── antmicro_artix_dc_scm
├── antmicro_datacenter_ddr4_test_board ├── antmicro_datacenter_ddr4_test_board
├── antmicro_lpddr4_test_board ├── antmicro_lpddr4_test_board

7
litex_boards/platforms/analog_pocket.py
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@ -15,6 +15,13 @@ _io_physical_litex = [
("clk74a", 0, Pins("V15"), IOStandard("3.3-V LVCMOS")), ("clk74a", 0, Pins("V15"), IOStandard("3.3-V LVCMOS")),
("clk74b", 0, Pins("H16"), IOStandard("1.8 V")), ("clk74b", 0, Pins("H16"), IOStandard("1.8 V")),
# Serial.
("serial", 0,
Subsignal("tx", Pins("K21")),
Subsignal("rx", Pins("K22")),
IOStandard("1.8V")
),
# SDR SDRAM # SDR SDRAM
("sdram_clock", 0, Pins("G12"), IOStandard("1.8V")), ("sdram_clock", 0, Pins("G12"), IOStandard("1.8V")),
("sdram", 0, ("sdram", 0,