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Merge pull request #114 from kbeckmann/versa_eth_phy 

versa_ecp5: Add --eth-phy to select ethernet phy
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enjoy-digital 2020-10-12 12:48:25 +02:00 committed by GitHub
parent fcf3e44e0e 5e67853a21
commit c2500e6649
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 11 additions and 14 deletions
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litex_boards/targets/versa_ecp5.py
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@ -78,7 +78,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(75e6), device="LFE5UM5G", with_ethernet=False, with_etherbone=False, toolchain="trellis", **kwargs): def __init__(self, sys_clk_freq=int(75e6), device="LFE5UM5G", with_ethernet=False, with_etherbone=False, eth_phy=0, toolchain="trellis", **kwargs):
platform = versa_ecp5.Platform(toolchain=toolchain, device=device) platform = versa_ecp5.Platform(toolchain=toolchain, device=device)
# FIXME: adapt integrated rom size for Microwatt # FIXME: adapt integrated rom size for Microwatt
@ -112,21 +112,16 @@ class BaseSoC(SoCCore):
l2_cache_reverse = True l2_cache_reverse = True
) )
# Ethernet --------------------------------------------------------------------------------- # Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet: if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII( self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"), clock_pads = self.platform.request("eth_clocks", eth_phy),
pads = self.platform.request("eth")) pads = self.platform.request("eth", eth_phy))
self.add_csr("ethphy") self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy) if with_ethernet:
self.add_ethernet(phy=self.ethphy)
# Etherbone -------------------------------------------------------------------------------- if with_etherbone:
if with_etherbone: self.add_etherbone(phy=self.ethphy)
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy)
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser( self.submodules.leds = LedChaser(
@ -148,6 +143,7 @@ def main():
parser.add_argument("--device", default="LFE5UM5G", help="ECP5 device (LFE5UM5G (default) or LFE5UM)") parser.add_argument("--device", default="LFE5UM5G", help="ECP5 device (LFE5UM5G (default) or LFE5UM)")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY 0 or 1 (default=0)")
args = parser.parse_args() args = parser.parse_args()
assert not (args.with_ethernet and args.with_etherbone) assert not (args.with_ethernet and args.with_etherbone)
@ -155,6 +151,7 @@ def main():
device = args.device, device = args.device,
with_ethernet = args.with_ethernet, with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone, with_etherbone = args.with_etherbone,
eth_phy = args.eth_phy,
toolchain = args.toolchain, toolchain = args.toolchain,
**soc_sdram_argdict(args)) **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))