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siglent_sds1104xe: Expose ethphy (to allow correct .dts generation).

This commit is contained in:
Florent Kermarrec 2021-04-29 11:02:13 +02:00
parent 7d651a9a17
commit c28a161392
1 changed files with 6 additions and 7 deletions
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13
litex_boards/targets/siglent_sds1104xe.py
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@ -107,15 +107,14 @@ class BaseSoC(SoCCore):
from liteeth.frontend.etherbone import LiteEthEtherbone
# Ethernet PHY
ethphy = LiteEthPHYMII(
self.submodules.ethphy = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.submodules += ethphy
etherbone_ip_address = convert_ip("192.168.1.51")
etherbone_mac_address = 0x10e2d5000001
# Ethernet MAC
self.submodules.ethmac = LiteEthMAC(phy=ethphy, dw=8,
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=8,
interface = "hybrid",
endianness = self.cpu.endianness,
hw_mac = etherbone_mac_address)
@ -137,10 +136,10 @@ class BaseSoC(SoCCore):
self.add_wb_master(self.etherbone.wishbone.bus)
# Timing constraints
eth_rx_clk = ethphy.crg.cd_eth_rx.clk
eth_tx_clk = ethphy.crg.cd_eth_tx.clk
self.platform.add_period_constraint(eth_rx_clk, 1e9/ethphy.rx_clk_freq)
self.platform.add_period_constraint(eth_tx_clk, 1e9/ethphy.tx_clk_freq)
eth_rx_clk = self.ethphy.crg.cd_eth_rx.clk
eth_tx_clk = self.ethphy.crg.cd_eth_tx.clk
self.platform.add_period_constraint(eth_rx_clk, 1e9/self.ethphy.rx_clk_freq)
self.platform.add_period_constraint(eth_tx_clk, 1e9/self.ethphy.tx_clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
# Video ------------------------------------------------------------------------------------