siglent_sds1104xe: Expose ethphy (to allow correct .dts generation).
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7d651a9a17
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@ -107,15 +107,14 @@ class BaseSoC(SoCCore):
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from liteeth.frontend.etherbone import LiteEthEtherbone
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from liteeth.frontend.etherbone import LiteEthEtherbone
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# Ethernet PHY
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# Ethernet PHY
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ethphy = LiteEthPHYMII(
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self.submodules.ethphy = LiteEthPHYMII(
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clock_pads = self.platform.request("eth_clocks"),
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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pads = self.platform.request("eth"))
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self.submodules += ethphy
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etherbone_ip_address = convert_ip("192.168.1.51")
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etherbone_ip_address = convert_ip("192.168.1.51")
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etherbone_mac_address = 0x10e2d5000001
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etherbone_mac_address = 0x10e2d5000001
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# Ethernet MAC
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# Ethernet MAC
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self.submodules.ethmac = LiteEthMAC(phy=ethphy, dw=8,
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self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=8,
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interface = "hybrid",
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interface = "hybrid",
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endianness = self.cpu.endianness,
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endianness = self.cpu.endianness,
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hw_mac = etherbone_mac_address)
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hw_mac = etherbone_mac_address)
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@ -137,10 +136,10 @@ class BaseSoC(SoCCore):
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self.add_wb_master(self.etherbone.wishbone.bus)
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self.add_wb_master(self.etherbone.wishbone.bus)
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# Timing constraints
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# Timing constraints
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eth_rx_clk = ethphy.crg.cd_eth_rx.clk
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eth_rx_clk = self.ethphy.crg.cd_eth_rx.clk
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eth_tx_clk = ethphy.crg.cd_eth_tx.clk
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eth_tx_clk = self.ethphy.crg.cd_eth_tx.clk
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self.platform.add_period_constraint(eth_rx_clk, 1e9/ethphy.rx_clk_freq)
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self.platform.add_period_constraint(eth_rx_clk, 1e9/self.ethphy.rx_clk_freq)
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self.platform.add_period_constraint(eth_tx_clk, 1e9/ethphy.tx_clk_freq)
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self.platform.add_period_constraint(eth_tx_clk, 1e9/self.ethphy.tx_clk_freq)
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self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
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self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
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# Video ------------------------------------------------------------------------------------
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# Video ------------------------------------------------------------------------------------
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