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trenz_tec0117: Get BIOS XiP from SPI Flash working, remove CPU variant force since can now fit default VexRiscv config.

This commit is contained in:
Florent Kermarrec 2021-07-14 12:49:03 +02:00
parent 132feaf3e8
commit c369f4bb7f
1 changed files with 13 additions and 47 deletions
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60
litex_boards/targets/trenz_tec0117.py
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@ -64,14 +64,9 @@ class BaseSoC(SoCCore):
def __init__(self, bios_flash_offset, sys_clk_freq=int(25e6), sdram_rate="1:1", **kwargs):
platform = tec0117.Platform()
# Use custom default configuration to fit in LittleBee.
kwargs["integrated_sram_size"] = 0x1000
kwargs["integrated_rom_size"] = 0x6000
if kwargs.get("cpu_type", "vexriscv") == "vexriscv":
kwargs["cpu_variant"] = "lite"
# Set CPU variant / reset address
kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
# Put BIOS in SPIFlash to save BlockRAMs.
kwargs["integrated_rom_size"] = 0
kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
@ -86,12 +81,11 @@ class BaseSoC(SoCCore):
self.add_spi_flash(mode="1x", dummy_cycles=8)
# Add ROM linker region --------------------------------------------------------------------
# FIXME: SPI Flash does not seem responding, power down set after loading bitstream?
#self.bus.add_region("rom", SoCRegion(
# origin = self.mem_map["spiflash"] + bios_flash_offset,
# size = 32*kB,
# linker = True)
#)
self.bus.add_region("rom", SoCRegion(
origin = self.mem_map["spiflash"] + bios_flash_offset,
size = 32*kB,
linker = True)
)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
@ -129,34 +123,6 @@ class BaseSoC(SoCCore):
# Flash --------------------------------------------------------------------------------------------
def flash(bios_flash_offset):
# Prepare Flash image.
# --------------------
bitstream = open("build/tec0117/gateware/impl/pnr/project.bin", "rb")
bios = open("build/tec0117/software/bios/bios.bin", "rb")
image = open("build/tec0117/image.bin", "wb")
# Copy Bitstream at 0.
blength = 0
while True:
b = bitstream.read(1)
if not b:
break
else:
image.write(b)
blength += 1
# Check Bitstream/BIOS overlap.
if blength > bios_flash_offset:
raise ValueError(f"Bitstream/BIOS overlap 0x{blength:08x} vs 0x{bios_flash_offset:08x}, increase BIOS Flash offset.")
# Fill Gap between Bitstream/BIOS with zeroes.
for i in range(bios_flash_offset - blength):
image.write(0x00.to_bytes(1, "big"))
# Copy BIOS at bios_flash_offset
while True:
b = bios.read(1)
if not b:
break
else:
image.write(b)
# Create FTDI <--> SPI Flash proxy bitstream and load it.
# -------------------------------------------------------
platform = tec0117.Platform()
@ -180,10 +146,10 @@ def flash(bios_flash_offset):
dev.TIMINGS["chip"] = (4, 60) # Chip is too slow
print("Erasing flash...")
dev.erase(0, -1)
with open("build/tec0117/image.bin", "rb") as f:
image = f.read()
with open("build/trenz_tec0117/software/bios/bios.bin", "rb") as f:
bios = f.read()
print("Programming flash...")
dev.write(0, image)
dev.write(bios_flash_offset, bios)
# Build --------------------------------------------------------------------------------------------
@ -191,7 +157,7 @@ def main():
parser = argparse.ArgumentParser(description="LiteX SoC on TEC0117")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--bios-flash-offset", default=0x80000, help="BIOS offset in SPI Flash (0x00000 default)")
parser.add_argument("--bios-flash-offset", default=0x0000, help="BIOS offset in SPI Flash (0x00000 default)")
parser.add_argument("--flash", action="store_true", help="Flash Bitstream and BIOS")
parser.add_argument("--sys-clk-freq", default=25e6, help="System clock frequency (default: 25MHz)")
builder_args(parser)
@ -211,9 +177,9 @@ def main():
prog.load_bitstream(os.path.join(builder.gateware_dir, "impl", "pnr", "project.fs"))
if args.flash:
# flash(args.bios_flash_offset) FIXME.
prog = soc.platform.create_programmer()
prog.flash(0, os.path.join(builder.gateware_dir, "impl", "pnr", "project.fs"))
flash(args.bios_flash_offset)
if __name__ == "__main__":
main()