Add colorlight i5 board support
This commit is contained in:
Kaz Kojima
parent
5fd04a97ea
commit
c3fa0eac8b
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Kazumoto Kojima <kkojima@rr.iij4u.or.jp>
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# SPDX-License-Identifier: BSD-2-Clause
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# The Colorlight i5 PCB and IOs have been documented by @wuxx
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# https://github.com/wuxx/Colorlight-FPGA-Projects
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice.programmer import EcpDapProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io_v7_0 = [ # Documented by @smunaut
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# Clk
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("clk25", 0, Pins("P3"), IOStandard("LVCMOS33")),
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# Led
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("user_led_n", 0, Pins("U16"), IOStandard("LVCMOS33")),
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# Reset button
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("cpu_reset_n", 0, Pins("K18"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("J17")),
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Subsignal("rx", Pins("H18")),
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IOStandard("LVCMOS33")
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),
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# SPIFlash (GD25Q16CSIG)
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("spiflash", 0,
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Subsignal("cs_n", Pins("R2")),
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# https://github.com/m-labs/nmigen-boards/pull/38
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#Subsignal("clk", Pins("")), driven through USRMCLK
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Subsignal("mosi", Pins("W2")),
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Subsignal("miso", Pins("V2")),
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IOStandard("LVCMOS33"),
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),
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# SDRAM SDRAM (EM638325-6H)
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("sdram_clock", 0, Pins("B9"), IOStandard("LVCMOS33")),
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("sdram", 0,
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Subsignal("a", Pins(
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"B13 C14 A16 A17 B16 B15 A14 A13",
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"A12 A11 B12")),
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Subsignal("dq", Pins(
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"D15 E14 E13 D12 E12 D11 C10 B17",
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"B8 A8 C7 A7 A6 B6 A5 B5",
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"D5 C5 D6 C6 E7 D7 E8 D8",
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"E9 D9 E11 C11 C12 D13 D14 C15")),
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Subsignal("we_n", Pins("A10")),
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Subsignal("ras_n", Pins("B10")),
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Subsignal("cas_n", Pins("A9")),
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#Subsignal("cs_n", Pins("")), # gnd
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#Subsignal("cke", Pins("")), # 3v3
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Subsignal("ba", Pins("B11 C8")), # sdram pin BA0 and BA1
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#Subsignal("dm", Pins("")), # gnd
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IOStandard("LVCMOS33"),
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Misc("SLEWRATE=FAST")
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),
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# RGMII Ethernet (B50612D)
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# The order of the two PHYs is swapped with the naming of the connectors
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# on the board so to match with the configuration of their PHYA[0] pins.
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("eth_clocks", 0,
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Subsignal("tx", Pins("G1")),
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Subsignal("rx", Pins("H2")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("P4")),
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Subsignal("mdio", Pins("P5")),
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Subsignal("mdc", Pins("N5")),
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Subsignal("rx_ctl", Pins("P2")),
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Subsignal("rx_data", Pins("K2 L1 N1 P1")),
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Subsignal("tx_ctl", Pins("K1")),
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Subsignal("tx_data", Pins("G2 H1 J1 J3")),
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IOStandard("LVCMOS33")
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),
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("eth_clocks", 1,
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Subsignal("tx", Pins("U19")),
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Subsignal("rx", Pins("L19")),
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IOStandard("LVCMOS33")
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),
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("eth", 1,
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Subsignal("rst_n", Pins("P4")),
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Subsignal("mdio", Pins("P5")),
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Subsignal("mdc", Pins("N5")),
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Subsignal("rx_ctl", Pins("M20")),
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Subsignal("rx_data", Pins("P20 N19 N20 M19")),
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Subsignal("tx_ctl", Pins("P19")),
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Subsignal("tx_data", Pins("U20 T19 T20 R20")),
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IOStandard("LVCMOS33")
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),
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]
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# From https://github.com/wuxx/Colorlight-FPGA-Projects/blob/master/schematic/i5_v6.0-extboard.pdf and
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# https://github.com/wuxx/Colorlight-FPGA-Projects/blob/master/doc/i5_extboard_v1.2_pinout.png
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_connectors_v7_0 = [
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("pmode", "C17 B18 B20 F20 A18 A19 B19 D20"),
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("pmodf", "D1 C1 C2 E3 E2 D2 B1 A3"),
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]
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# PMODS --------------------------------------------------------------------------------------------
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def sdcard_pmod_io(pmod):
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return [
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# SDCard PMOD:
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# - https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
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("spisdcard", 0,
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Subsignal("clk", Pins(f"{pmod}:3")),
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Subsignal("mosi", Pins(f"{pmod}:1"), Misc("PULLMODE=UP")),
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Subsignal("cs_n", Pins(f"{pmod}:0"), Misc("PULLMODE=UP")),
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Subsignal("miso", Pins(f"{pmod}:2"), Misc("PULLMODE=UP")),
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Misc("SLEWRATE=FAST"),
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IOStandard("LVCMOS33"),
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),
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("sdcard", 0,
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Subsignal("data", Pins(f"{pmod}:2 {pmod}:4 {pmod}:5 {pmod}:0"), Misc("PULLMODE=UP")),
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Subsignal("cmd", Pins(f"{pmod}:1"), Misc("PULLMODE=UP")),
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Subsignal("clk", Pins(f"{pmod}:3")),
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Subsignal("cd", Pins(f"{pmod}:6")),
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#Misc("SLEWRATE=FAST"),
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IOStandard("LVCMOS33"),
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),
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]
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_sdcard_pmod_io = sdcard_pmod_io("pmode") # SDCARD PMOD on P3.
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk25"
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default_clk_period = 1e9/25e6
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def __init__(self, revision="7.0", toolchain="trellis"):
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assert revision in ["7.0"]
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self.revision = revision
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device = {"7.0": "LFE5U-25F-6BG381C"}[revision]
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io = {"7.0": _io_v7_0}[revision]
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connectors = {"7.0": _connectors_v7_0}[revision]
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LatticePlatform.__init__(self, device, io, connectors=connectors, toolchain=toolchain)
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def create_programmer(self):
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return EcpDapProgrammer()
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def do_finalize(self, fragment):
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LatticePlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/25e6)
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self.add_period_constraint(self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9/125e6)
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self.add_period_constraint(self.lookup_request("eth_clocks:rx", 1, loose=True), 1e9/125e6)
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@ -0,0 +1,241 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Kazumoto Kojima <kkojima@rr.iij4u.or.jp>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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import sys
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.io import DDROutput
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from litex_boards.platforms import colorlight_i5
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from litex.build.tools import write_to_file
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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from litex.soc.cores.clock import *
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from litex.soc.cores.spi_flash import SpiFlash
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from litex.soc.cores.spi import SPIMaster
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.interconnect.csr import *
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from litex.soc.cores.prbs import *
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from litedram.modules import M12L64322A
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
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# PRBS -------------------------------------------------------------------------------------------
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class _PRBSSource(Module, AutoCSR):
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def __init__(self):
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self.submodules.prbs = prbs = PRBS31Generator(32)
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self.data = CSRStatus(32)
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self.comb += [
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self.data.status.eq(prbs.o)
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]
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, use_internal_osc=False, with_usb_pll=False, sdram_rate="1:1"):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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if sdram_rate == "1:2":
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True)
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else:
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self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
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# # #
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# Clk / Rst
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if not use_internal_osc:
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clk = platform.request("clk25")
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clk_freq = 25e6
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else:
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clk = Signal()
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div = 5
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self.specials += Instance("OSCG",
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p_DIV = div,
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o_OSC = clk)
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clk_freq = 310e6/div
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rst_n = platform.request("cpu_reset_n")
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# PLL
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self.submodules.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(~rst_n | self.rst)
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pll.register_clkin(clk, clk_freq)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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if sdram_rate == "1:2":
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) # Idealy 90° but needs to be increased.
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else:
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180) # Idealy 90° but needs to be increased.
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# USB PLL
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if with_usb_pll:
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self.submodules.usb_pll = usb_pll = ECP5PLL()
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self.comb += usb_pll.reset.eq(~rst_n | self.rst)
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usb_pll.register_clkin(clk, clk_freq)
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self.clock_domains.cd_usb_12 = ClockDomain()
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self.clock_domains.cd_usb_48 = ClockDomain()
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usb_pll.create_clkout(self.cd_usb_12, 12e6, margin=0)
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usb_pll.create_clkout(self.cd_usb_48, 48e6, margin=0)
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# SDRAM clock
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sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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mem_map = {**SoCCore.mem_map, **{"spiflash": 0xd0000000}}
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def __init__(self, board="i5", revision="7.0", sys_clk_freq=60e6, with_ethernet=False, with_etherbone=False, local_ip="", remote_ip="", eth_phy=0, use_internal_osc=False, sdram_rate="1:1", with_prbs=False, **kwargs):
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board = board.lower()
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assert board in ["i5"]
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if board == "i5":
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platform = colorlight_i5.Platform(revision=revision)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, int(sys_clk_freq),
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ident = "LiteX SoC on Colorlight " + board.upper(),
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
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self.submodules.crg = _CRG(platform, sys_clk_freq, use_internal_osc=use_internal_osc, with_usb_pll=with_usb_pll, sdram_rate=sdram_rate)
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# Leds -------------------------------------------------------------------------------------
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ledn = platform.request_all("user_led_n")
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self.submodules.leds = LedChaser(pads=ledn, sys_clk_freq=sys_clk_freq)
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self.add_csr("leds")
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# SPI Flash --------------------------------------------------------------------------------
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self.add_spi_flash(mode="1x", dummy_cycles=8)
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self.add_constant("SPIFLASH_PAGE_SIZE", 256)
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self.add_constant("SPIFLASH_SECTOR_SIZE", 4096)
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
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self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
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# if board == "i5" and revision == "7.0":
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sdram_cls = M12L64322A # compat with EM638325-6H
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = sdram_cls(sys_clk_freq, sdram_rate),
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origin = self.mem_map["main_ram"],
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size = kwargs.get("max_sdram_size", 0x40000000),
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l2_cache_size = kwargs.get("l2_size", 8192),
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l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
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l2_cache_reverse = True
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)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.submodules.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks", eth_phy),
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pads = self.platform.request("eth", eth_phy))
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self.add_csr("ethphy")
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self.add_constant("TARGET_BIOS_INIT", 1)
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy)
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if local_ip:
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local_ip = local_ip.split(".")
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self.add_constant("LOCALIP1", int(local_ip[0]))
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self.add_constant("LOCALIP2", int(local_ip[1]))
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self.add_constant("LOCALIP3", int(local_ip[2]))
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self.add_constant("LOCALIP4", int(local_ip[3]))
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if remote_ip:
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remote_ip = remote_ip.split(".")
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self.add_constant("REMOTEIP1", int(remote_ip[0]))
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self.add_constant("REMOTEIP2", int(remote_ip[1]))
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self.add_constant("REMOTEIP3", int(remote_ip[2]))
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self.add_constant("REMOTEIP4", int(remote_ip[3]))
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# PRBS -------------------------------------------------------------------------------------
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if with_prbs:
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self.submodules.prbs = _PRBSSource()
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self.add_csr("prbs")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Colorlight i5")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--board", default="i5", help="Board type: i5 (default)")
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parser.add_argument("--revision", default="7.0", type=str, help="Board revision: 7.0 (default)")
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parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default: 60MHz)")
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parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
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parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
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parser.add_argument("--remote-ip", default="192.168.1.100", help="Remote IP address of TFTP server")
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parser.add_argument("--local-ip", default="192.168.1.50", help="Local IP address")
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parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
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parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
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parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY: 0 (default) or 1")
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parser.add_argument("--use-internal-osc", action="store_true", help="Use internal oscillator")
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parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate")
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parser.add_argument("--l2-size", default=8192, type=int, help="L2 cache size")
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parser.add_argument("--with-prbs", action="store_true", help="Enable PRBS support")
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builder_args(parser)
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soc_core_args(parser)
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trellis_args(parser)
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args = parser.parse_args()
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assert not (args.with_ethernet and args.with_etherbone)
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soc = BaseSoC(board=args.board, revision=args.revision,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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local_ip = args.local_ip,
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remote_ip = args.remote_ip,
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eth_phy = args.eth_phy,
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use_internal_osc = args.use_internal_osc,
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sdram_rate = args.sdram_rate,
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l2_size = args.l2_size,
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with_prbs = args.with_prbs,
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**soc_core_argdict(args)
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)
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assert not (args.with_spi_sdcard and args.with_sdcard)
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soc.platform.add_extension(colorlight_i5._sdcard_pmod_io)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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if args.with_ethernet:
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os.makedirs(os.path.join(builder.software_dir, "include/generated"),
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exist_ok=True)
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write_to_file(
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os.path.join(builder.software_dir, "include/generated", "target.h"),
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"// Colorlight i5 needs this to disable TX data to clock delay.\n"
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"#define TARGET_BIOS_INIT_FUNC() mdio_write(0, 0x1c, 0x8c00)")
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builder.build(**trellis_argdict(args), run=args.build)
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if args.load:
|
||||
prog = soc.platform.create_programmer()
|
||||
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
Loading…
Reference in New Issue