fixed zynq7000 integration; introduced option to add the processing-system as slave to the SoC
This commit is contained in:
mkuhn99
parent
6f7716adbb
commit
c489347a51
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@ -19,18 +19,16 @@ from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.led import LedChaser
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from litex.soc.integration.soc import SoCRegion
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# CRG ----------------------------------------------------------------------------------------------
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, use_ps7_clk=False):
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def __init__(self, platform, sys_clk_freq, use_ps7_clk=False):
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self.rst = Signal()
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_sys = ClockDomain()
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# # #
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# # #
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if use_ps7_clk:
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if use_ps7_clk:
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assert sys_clk_freq == 100e6
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self.comb += ClockSignal("sys").eq(ClockSignal("ps7"))
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self.comb += ClockSignal("sys").eq(ClockSignal("ps7"))
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self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst)
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self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst)
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else:
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else:
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@ -43,55 +41,226 @@ class _CRG(LiteXModule):
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# BaseSoC ------------------------------------------------------------------------------------------
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=100e6, with_led_chaser=True, **kwargs):
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def __init__(self, sys_clk_freq=int(100e6), variant="z7-10", with_ps7=False, with_led_chaser=True, **kwargs):
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platform = digilent_zybo_z7.Platform()
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platform = digilent_zybo_z7.Platform()
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self.builder = None
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# CRG --------------------------------------------------------------------------------------
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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use_ps7_clk = (kwargs.get("cpu_type", None) == "zynq7000")
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self.crg = _CRG(platform, sys_clk_freq, use_ps7_clk)
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# SoCCore ----------------------------------------------------------------------------------
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# SoCCore ----------------------------------------------------------------------------------
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if kwargs["uart_name"] == "serial":
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if kwargs["uart_name"] == "serial":
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kwargs["uart_name"] = "usb_uart" # Use USB-UART Pmod on JB.
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kwargs["uart_name"] = "usb_uart" # Use USB-UART Pmod on JB.
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if kwargs.get("cpu_type", None) == "zynq7000":
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kwargs["integrated_sram_size"] = 0x0
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kwargs["with_uart"] = False
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self.mem_map = {
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'csr': 0x4000_0000, # Zynq GP0 default
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}
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Zybo Z7", **kwargs)
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Zybo Z7", **kwargs)
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# Zynq7000 Integration ---------------------------------------------------------------------
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# Zynq7000 Integration ---------------------------------------------------------------------
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if kwargs.get("cpu_type", None) == "zynq7000":
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if kwargs.get("cpu_type", None) == "zynq7000":
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# Get and set the pre-generated .xci FIXME: change location? add it to the repository?
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self.cpu.use_rom = True
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os.system("wget https://github.com/litex-hub/litex-boards/files/8339591/zybo_z7_ps7.txt)")
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os.makedirs("xci", exist_ok=True)
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if variant == "z7-10":
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os.system("mv zybo_z7_ps7.txt xci/zybo_z7_ps7.xci")
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# Get and set the pre-generated .xci FIXME: change location? add it to the repository? Make config
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self.cpu.set_ps7_xci("xci/zybo_z7_ps7.xci")
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os.makedirs("xci", exist_ok=True)
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os.system("wget https://github.com/litex-hub/litex-boards/files/8339591/zybo_z7_ps7.txt")
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os.system("mv zybo_z7_ps7.txt xci/zybo_z7_ps7.xci")
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self.cpu.set_ps7_xci("xci/zybo_z7_ps7.xci")
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else:
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self.cpu.set_ps7(name="ps", config = platform.ps7_config)
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# Connect AXI GP0 to the SoC with base address of 0x43c00000 (default one)
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# Connect AXI GP0 to the SoC with base address of 0x40000000 (default one)
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wb_gp0 = wishbone.Interface()
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wb_gp0 = wishbone.Interface()
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self.submodules += axi.AXI2Wishbone(
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self.submodules += axi.AXI2Wishbone(
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axi = self.cpu.add_axi_gp_master(),
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axi = self.cpu.add_axi_gp_master(),
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wishbone = wb_gp0,
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wishbone = wb_gp0,
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base_address = 0x43c00000)
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base_address = 0x40000000)
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self.bus.add_master(master=wb_gp0)
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self.bus.add_master(master=wb_gp0)
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#TODO memory size dependend on board variant
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self.bus.add_region("sram", SoCRegion(
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origin = self.cpu.mem_map["sram"],
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size = 512 * 1024 * 1024 - self.cpu.mem_map["sram"])
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)
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self.bus.add_region("rom", SoCRegion(
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origin = self.cpu.mem_map["rom"],
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size = 256 * 1024 * 1024 // 8,
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linker = True)
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)
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self.constants["CONFIG_CLOCK_FREQUENCY"] = 666666687
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self.bus.add_region("flash", SoCRegion(origin=0xFC00_0000, size=0x4_0000, mode="rwx"))
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# PS7 as Slave Integration ---------------------------------------------------------------------
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elif with_ps7:
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#TODO: ps7_slave for each variant
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if variant == "z7-20":
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self.add_ps7()
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self.add_axi_gp_slave()
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# Leds -------------------------------------------------------------------------------------
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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if with_led_chaser:
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self.leds = LedChaser(
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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sys_clk_freq = sys_clk_freq)
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def finalize(self, *args, **kwargs):
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super(BaseSoC, self).finalize(*args, **kwargs)
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if self.cpu_type != "zynq7000":
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return
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libxil_path = os.path.join(self.builder.software_dir, 'libxil')
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os.makedirs(os.path.realpath(libxil_path), exist_ok=True)
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lib = os.path.join(libxil_path, 'embeddedsw')
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if not os.path.exists(lib):
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os.system("git clone --depth 1 https://github.com/Xilinx/embeddedsw {}".format(lib))
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os.makedirs(os.path.realpath(self.builder.include_dir), exist_ok=True)
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for header in [
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'XilinxProcessorIPLib/drivers/uartps/src/xuartps_hw.h',
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'lib/bsp/standalone/src/common/xil_types.h',
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'lib/bsp/standalone/src/common/xil_assert.h',
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'lib/bsp/standalone/src/common/xil_io.h',
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'lib/bsp/standalone/src/common/xil_printf.h',
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'lib/bsp/standalone/src/common/xstatus.h',
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'lib/bsp/standalone/src/common/xdebug.h',
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'lib/bsp/standalone/src/arm/cortexa9/xpseudo_asm.h',
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'lib/bsp/standalone/src/arm/cortexa9/xreg_cortexa9.h',
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'lib/bsp/standalone/src/arm/cortexa9/xil_cache.h',
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'lib/bsp/standalone/src/arm/cortexa9/xparameters_ps.h',
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'lib/bsp/standalone/src/arm/cortexa9/xil_errata.h',
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'lib/bsp/standalone/src/arm/cortexa9/xtime_l.h',
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'lib/bsp/standalone/src/arm/common/xil_exception.h',
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'lib/bsp/standalone/src/arm/common/gcc/xpseudo_asm_gcc.h',
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]:
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shutil.copy(os.path.join(lib, header), self.builder.include_dir)
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write_to_file(os.path.join(self.builder.include_dir, 'bspconfig.h'),
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'#define FPU_HARD_FLOAT_ABI_ENABLED 1')
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write_to_file(os.path.join(self.builder.include_dir, 'xparameters.h'), '''
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#ifndef __XPARAMETERS_H
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#define __XPARAMETERS_H
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#include "xparameters_ps.h"
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#define STDOUT_BASEADDRESS XPS_UART1_BASEADDR
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#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
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#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
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#endif
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''')
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def add_ps7(self):
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ps7_tcl = []
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ps7_name = "processing_system"
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ps7_tcl.append(f"set ps7 [create_ip -vendor xilinx.com -name processing_system7 -module_name {ps7_name}]")
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ps7_tcl.append("set_property -dict [list \\")
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for config, value in self.platform.ps7_config.items():
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ps7_tcl.append("CONFIG.{} {} \\".format(config, '{{' + str(value) + '}}'))
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ps7_tcl.append(f"] [get_ips {ps7_name}]")
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ps7_tcl += [
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f"upgrade_ip [get_ips {ps7_name}]",
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f"generate_target all [get_ips {ps7_name}]",
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f"synth_ip [get_ips {ps7_name}]"
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]
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self.platform.toolchain.pre_synthesis_commands += ps7_tcl
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def add_axi_gp_slave(self):
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axi_gpn = axi.AXIInterface(data_width=32, address_width=32, id_width=12)
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#TODO: better mapping/ Different Regions for IOP and DDR
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aw_address = Signal(32)
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ar_address = Signal(32)
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#FIXME: define offsets with csr register?
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self.comb += If(axi_gpn.aw.addr < 0x1ffbffff,
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## DDR
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aw_address.eq(axi_gpn.aw.addr + 0x0008_0000)
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).Else(
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## IOP Register
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aw_address.eq(axi_gpn.aw.addr + 0xe000_0000))
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self.comb += If(axi_gpn.ar.addr < 0x1ffbffff,
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## DDR
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ar_address.eq(axi_gpn.ar.addr + 0x0008_0000)
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).Else(
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## IOP Register
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ar_address.eq(axi_gpn.ar.addr + 0xe000_0000))
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# generate instance of ps7 with ports for axi_s_gp0
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ps7_axi_s_gp0 = Instance("processing_system" ,
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#o_S_AXI_GP0_ARESETN = axi_gpn.a.resetn,
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o_S_AXI_GP0_ARREADY = axi_gpn.ar.ready,
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o_S_AXI_GP0_AWREADY = axi_gpn.aw.ready,
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o_S_AXI_GP0_BVALID = axi_gpn.b.valid,
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o_S_AXI_GP0_RLAST = axi_gpn.r.last,
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o_S_AXI_GP0_RVALID = axi_gpn.r.valid,
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o_S_AXI_GP0_WREADY = axi_gpn.w.ready,
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o_S_AXI_GP0_BRESP = axi_gpn.b.resp,
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o_S_AXI_GP0_RRESP = axi_gpn.r.resp,
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o_S_AXI_GP0_RDATA = axi_gpn.r.data,
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o_S_AXI_GP0_BID = axi_gpn.b.id,
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o_S_AXI_GP0_RID = axi_gpn.r.id,
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i_S_AXI_GP0_ACLK = ClockSignal("sys"),
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i_S_AXI_GP0_ARVALID = axi_gpn.ar.valid,
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i_S_AXI_GP0_AWVALID = axi_gpn.aw.valid,
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i_S_AXI_GP0_BREADY = axi_gpn.b.ready,
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i_S_AXI_GP0_RREADY = axi_gpn.r.ready,
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i_S_AXI_GP0_WLAST = axi_gpn.w.last,
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i_S_AXI_GP0_WVALID = axi_gpn.w.valid,
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i_S_AXI_GP0_ARBURST = axi_gpn.ar.burst,
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i_S_AXI_GP0_ARLOCK = axi_gpn.ar.lock,
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i_S_AXI_GP0_ARSIZE = axi_gpn.ar.size,
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i_S_AXI_GP0_AWBURST = axi_gpn.aw.burst,
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i_S_AXI_GP0_AWLOCK = axi_gpn.aw.lock,
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i_S_AXI_GP0_AWSIZE = axi_gpn.aw.size,
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i_S_AXI_GP0_ARPROT = axi_gpn.ar.prot,
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i_S_AXI_GP0_AWPROT = axi_gpn.aw.prot,
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i_S_AXI_GP0_ARADDR = ar_address,
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i_S_AXI_GP0_AWADDR = aw_address,
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i_S_AXI_GP0_WDATA = axi_gpn.w.data,
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i_S_AXI_GP0_ARCACHE = axi_gpn.ar.cache,
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i_S_AXI_GP0_ARLEN = axi_gpn.ar.len,
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i_S_AXI_GP0_ARQOS = axi_gpn.ar.qos,
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i_S_AXI_GP0_AWCACHE = axi_gpn.aw.cache,
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i_S_AXI_GP0_AWLEN = axi_gpn.aw.len,
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i_S_AXI_GP0_AWQOS = axi_gpn.aw.qos,
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i_S_AXI_GP0_WSTRB = axi_gpn.w.strb,
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i_S_AXI_GP0_ARID = axi_gpn.ar.id,
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i_S_AXI_GP0_AWID = axi_gpn.aw.id,
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i_S_AXI_GP0_WID = axi_gpn.w.id,
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)
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self.specials += ps7_axi_s_gp0
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self.bus.add_slave(name="main_ram",slave=axi_gpn, region=SoCRegion(origin=0x4000_0000, size=0x2000_0000, mode="rwx"))
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# Build --------------------------------------------------------------------------------------------
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# Build --------------------------------------------------------------------------------------------
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def main():
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def main():
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from litex.build.parser import LiteXArgumentParser
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXArgumentParser(platform=digilent_zybo_z7.Platform, description="LiteX SoC on Zybo Z7.")
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parser = LiteXSoCArgumentParser(description="LiteX SoC on Zybo Z7")
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parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build design.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
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target_group.add_argument("--variant", default="z7-10", help="Board variant (z7-10 or z7-20).")
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target_group.add_argument("--with-ps7", action="store_true", help="Add the PS as slave.")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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args = parser.parse_args()
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soc = BaseSoC(
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soc = BaseSoC(
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sys_clk_freq = args.sys_clk_freq,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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**parser.soc_argdict
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variant = args.variant,
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with_ps7 = args.with_ps7,
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**soc_core_argdict(args)
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)
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)
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builder = Builder(soc, **parser.builder_argdict)
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builder = Builder(soc, **builder_argdict(args))
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if args.cpu_type == "zynq7000":
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soc.builder = builder
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builder.add_software_package('libxil')
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builder.add_software_library('libxil')
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if args.build:
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if args.build:
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builder.build(**parser.toolchain_argdict)
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builder.build(**parser.toolchain_argdict)
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if args.load:
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if args.load:
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prog = soc.platform.create_programmer()
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"), device=1)
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"), device=1)
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