Added QMTech EP4CE55 board - almost identical to EP4CE15 board but bigger FPGA.
This commit is contained in:
Alastair M. Robinson
parent
8a33c2aa31
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Basel Sayeh <Basel.Sayeh@hotmail.com>
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# Copyright (c) 2021 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.altera import AlteraPlatform
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from litex.build.altera.programmer import USBBlaster
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk
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("clk50", 0, Pins("T2"), IOStandard("3.3-V LVTTL")),
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# Button
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("key", 0, Pins("Y13"), IOStandard("3.3-V LVTTL")),
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("key", 1, Pins("W13"), IOStandard("3.3-V LVTTL")),
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# SPIFlash (W25Q64)
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("spiflash", 0,
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# clk
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Subsignal("cs_n", Pins("E2")),
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Subsignal("clk", Pins("K2")),
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Subsignal("mosi", Pins("D1")),
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Subsignal("miso", Pins("E2")),
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IOStandard("3.3-V LVTTL"),
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),
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# SDR SDRAM
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("sdram_clock", 0, Pins("Y6"), IOStandard("3.3-V LVTTL")),
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("sdram", 0,
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Subsignal("a", Pins(
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"V2 V1 U2 U1 V3 V4 Y2 AA1",
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"Y3 V5 W1 Y4 V6")),
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Subsignal("ba", Pins("Y1 W2")),
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Subsignal("cs_n", Pins("AA3")),
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Subsignal("cke", Pins("W6")),
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Subsignal("ras_n", Pins("AB3")),
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Subsignal("cas_n", Pins("AA4")),
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Subsignal("we_n", Pins("AB4")),
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Subsignal("dq", Pins(
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"AA10 AB9 AA9 AB8 AA8 AB7 AA7 AB5",
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"Y7 W8 Y8 V9 V10 Y10 W10 V11")),
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Subsignal("dm", Pins("AA5 W7")),
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IOStandard("3.3-V LVTTL")
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),
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]
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# The connectors are named after the daughterboard, not the core board
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# because on the different core boards the names vary, but on the
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# daughterboard they stay the same, which we need to connect the
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# daughterboard peripherals to the core board.
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# On this board J2 is U7 and J3 is U8
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_connectors = [
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("J2", {
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# odd row even row
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7: "R1", 8: "R2",
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9: "P1", 10: "P2",
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11: "N1", 12: "N2",
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13: "M1", 14: "M2",
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15: "J1", 16: "J2",
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17: "H1", 18: "H2",
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19: "F1", 20: "F2",
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21: "E1", 22: "D2",
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23: "C1", 24: "C2",
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25: "B1", 26: "B2",
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27: "B3", 28: "A3",
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29: "B4", 30: "A4",
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31: "C4", 32: "C3",
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33: "B5", 34: "A5",
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35: "B6", 36: "A6",
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37: "B7", 38: "A7",
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39: "B8", 40: "A8",
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41: "B9", 42: "A9",
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43: "B10", 44: "A10",
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45: "B13", 46: "A13",
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47: "B14", 48: "A14",
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49: "B15", 50: "A15",
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51: "B16", 52: "A16",
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53: "B17", 54: "A17",
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55: "B18", 56: "A18",
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57: "B19", 58: "A19",
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59: "B20", 60: "A20",
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}),
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("J3", {
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# odd row even row
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7: "AA13", 8: "AB13",
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9: "AA14", 10: "AB14",
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11: "AA15", 12: "AB15",
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13: "AA16", 14: "AB16",
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15: "AA17", 16: "AB17",
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17: "AA18", 18: "AB18",
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19: "AA19", 20: "AB19",
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21: "AA20", 22: "AB20",
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23: "Y22", 24: "Y21",
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25: "W22", 26: "W21",
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27: "V22", 28: "V21",
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29: "U22", 30: "U21",
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31: "R22", 32: "R21",
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33: "P22", 34: "P21",
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35: "N22", 36: "N21",
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37: "M22", 38: "M21",
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39: "L22", 40: "L21",
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41: "K22", 42: "K21",
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43: "J22", 44: "J21",
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45: "H22", 46: "H21",
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47: "F22", 48: "F21",
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49: "E22", 50: "E21",
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51: "D22", 52: "D21",
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53: "C22", 54: "C21",
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55: "B22", 56: "B21",
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57: "N20", 58: "N19",
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59: "M20", 60: "M19",
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})
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(AlteraPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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core_resources = [
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("user_led", 0, Pins("E4"), IOStandard("3.3-V LVTTL")),
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("serial", 0,
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Subsignal("tx", Pins("J3:7"), IOStandard("3.3-V LVTTL")),
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Subsignal("rx", Pins("J3:8"), IOStandard("3.3-V LVTTL"))
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),
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]
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def __init__(self, with_daughterboard=False):
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device = "EP4CE55F23C8"
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io = _io
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connectors = _connectors
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if with_daughterboard:
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from litex_boards.platforms.qmtech_daughterboard import QMTechDaughterboard
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daughterboard = QMTechDaughterboard(IOStandard("3.3-V LVTTL"))
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io += daughterboard.io
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connectors += daughterboard.connectors
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else:
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io += self.core_resources
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AlteraPlatform.__init__(self, device, io, connectors)
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if with_daughterboard:
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# an ethernet pin takes K22, so make it available
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self.add_platform_command("set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
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def create_programmer(self):
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return USBBlaster()
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def do_finalize(self, fragment):
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AlteraPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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@ -0,0 +1,181 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Basel Sayeh <Basel.Sayeh@hotmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.io import DDROutput
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from litex_boards.platforms import qmtech_ep4ce55
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from litex.soc.cores.clock import CycloneIVPLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import W9825G6KH6
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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from litex.soc.cores.video import VideoVGAPHY
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from liteeth.phy.mii import LiteEthPHYMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_ethernet, with_vga, sdram_rate="1:1"):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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if sdram_rate == "1:2":
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True)
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else:
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self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
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if with_ethernet:
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self.clock_domains.cd_eth = ClockDomain()
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if with_vga:
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self.clock_domains.cd_vga = ClockDomain(reset_less=True)
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# # #
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# Clk / Rst
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clk50 = platform.request("clk50")
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# PLL
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self.submodules.pll = pll = CycloneIVPLL(speedgrade="-6")
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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if sdram_rate == "1:2":
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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# theoretically 90 degrees, but increase to relax timing
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pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180)
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else:
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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if with_ethernet:
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pll.create_clkout(self.cd_eth, 25e6)
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if with_vga:
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pll.create_clkout(self.cd_vga, 40e6)
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# SDRAM clock
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sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), with_daughterboard=False,
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with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
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with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False,
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ident_version=True, sdram_rate="1:1", **kwargs):
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platform = qmtech_ep4ce55.Platform(with_daughterboard=with_daughterboard)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on QMTECH EP4CE55" + (" + Daughterboard" if with_daughterboard else ""),
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ident_version = ident_version,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform,
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sys_clk_freq, with_ethernet or with_etherbone,
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with_video_terminal or with_video_framebuffer,
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sdram_rate=sdram_rate)
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
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self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = W9825G6KH6(sys_clk_freq, sdram_rate),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.submodules.ethphy = LiteEthPHYMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal or with_video_framebuffer:
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self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on QMTECH EP4CE55")
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parser.add_argument("--build", action="store_true", help="Build bitstream.")
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parser.add_argument("--load", action="store_true", help="Load bitstream.")
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parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
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parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
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parser.add_argument("--with-daughterboard", action="store_true", help="Board plugged into the QMTech daughterboard.")
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ethopts = parser.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
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parser.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
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sdopts = parser.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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parser.add_argument("--no-ident-version", action="store_false", help="Disable build time output.")
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viopts = parser.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (VGA).")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_daughterboard = args.with_daughterboard,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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eth_dynamic_ip = args.eth_dynamic_ip,
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ident_version = args.no_ident_version,
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with_video_terminal = args.with_video_terminal,
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with_video_framebuffer = args.with_video_framebuffer,
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sdram_rate = args.sdram_rate,
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**soc_core_argdict(args)
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)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".sof"))
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if __name__ == "__main__":
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main()
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