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platforms/xcu1525: update ddram1/2/3 pinout. 

Using https://github.com/d953i/Custom_Part_Data_Files/blob/master/Boards/Xilinx_BCU1525/BCU1525_DIMMx.xdc
This commit is contained in:
Florent Kermarrec 2020-09-20 21:07:00 +02:00
parent e5a144e9cd
commit c6610b4a3f
1 changed files with 21 additions and 21 deletions
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42
litex_boards/platforms/xcu1525.py
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@ -118,17 +118,19 @@ _io = [
Subsignal("act_n", Pins("AW25"), IOStandard("SSTL12_DCI")), Subsignal("act_n", Pins("AW25"), IOStandard("SSTL12_DCI")),
Subsignal("ba", Pins("AU24 AP26"), IOStandard("SSTL12_DCI")), Subsignal("ba", Pins("AU24 AP26"), IOStandard("SSTL12_DCI")),
Subsignal("bg", Pins("BC22 AW26"), IOStandard("SSTL12_DCI")), Subsignal("bg", Pins("BC22 AW26"), IOStandard("SSTL12_DCI")),
Subsignal("cas_n", Pins("AM25"), IOStandard("SSTL12_DCI")), Subsignal("ras_n", Pins("AN23"), IOStandard("SSTL12_DCI")), # A16
Subsignal("cas_n", Pins("AM25"), IOStandard("SSTL12_DCI")), # A15
Subsignal("we_n", Pins("AL25"), IOStandard("SSTL12_DCI")), # A14
Subsignal("cke", Pins("BB25"), IOStandard("SSTL12_DCI")), Subsignal("cke", Pins("BB25"), IOStandard("SSTL12_DCI")),
Subsignal("clk_n", Pins("AU25"), IOStandard("DIFF_SSTL12_DCI")), Subsignal("clk_n", Pins("AU25"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("clk_p", Pins("AT25"), IOStandard("DIFF_SSTL12_DCI")), Subsignal("clk_p", Pins("AT25"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("cs_n", Pins("AV23"), IOStandard("SSTL12_DCI")), Subsignal("cs_n", Pins("AV23"), IOStandard("SSTL12_DCI")),
Subsignal("dm", Pins("BE12 BE15 BC13 BB14 AV18 AW16 AP16 AM17"), Subsignal("dm", Pins("BE8 AY13 BA10 AN14 BE15 BB14 AW16 AM17"),
IOStandard("POD12_DCI")), IOStandard("POD12_DCI")),
Subsignal("dq", Pins( Subsignal("dq", Pins(
"BD9 BD7 BC7 BD8 BD10 BE10 BE7 BF7", " BD9 BD7 BC7 BD8 BD10 BE10 BE7 BF7",
"AU13 AV13 AW13 AW14 AU14 AY11 AV14 BA11", "AU13 AV13 AW13 AW14 AU14 AY11 AV14 BA11",
"BA12 BB12 BA13 BA14 BC9 BB9 BA7 BA8", "BA12 BB12 BA13 BA14 BC9 BB9 BA7 BA8",
"AN13 AR13 AM13 AP13 AM14 AR15 AL14 AT15", "AN13 AR13 AM13 AP13 AM14 AR15 AL14 AT15",
"BE13 BD14 BF12 BD13 BD15 BD16 BF14 BF13", "BE13 BD14 BF12 BD13 BD15 BD16 BF14 BF13",
"AY17 BA17 AY18 BA18 BA15 BB15 BC11 BD11", "AY17 BA17 AY18 BA18 BA15 BB15 BC11 BD11",
@ -137,18 +139,16 @@ _io = [
IOStandard("POD12_DCI"), IOStandard("POD12_DCI"),
Misc("PRE_EMPHASIS=RDRV_240"), Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")), Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dqs_n", Pins("BF9 BF8 AY15 AY12 BB10 BA9 AT13 AP14"), Subsignal("dqs_n", Pins("BF9 AY15 BB10 AT13 BE11 BC12 AW18 AR16"),
IOStandard("DIFF_POD12"), IOStandard("DIFF_POD12"),
Misc("PRE_EMPHASIS=RDRV_240"), Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")), Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dqs_p", Pins("BF10 BE8 AW15 AY13 BB11 BA10 AT14 AN14"), Subsignal("dqs_p", Pins("BF10 AW15 BB11 AT14 BE12 BC13 AV18 AP16"),
IOStandard("DIFF_POD12"), IOStandard("DIFF_POD12"),
Misc("PRE_EMPHASIS=RDRV_240"), Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")), Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("odt", Pins("AW23"), IOStandard("SSTL12_DCI")), Subsignal("odt", Pins("AW23"), IOStandard("SSTL12_DCI")),
Subsignal("ras_n", Pins("AN23"), IOStandard("SSTL12_DCI")),
Subsignal("reset_n", Pins("AR17"), IOStandard("LVCMOS12")), Subsignal("reset_n", Pins("AR17"), IOStandard("LVCMOS12")),
Subsignal("we_n", Pins("AL25"), IOStandard("SSTL12_DCI")),
Misc("SLEW=FAST") Misc("SLEW=FAST")
), ),
("ddram", 2, ("ddram", 2,
@ -159,12 +159,14 @@ _io = [
Subsignal("act_n", Pins("B31"), IOStandard("SSTL12_DCI")), Subsignal("act_n", Pins("B31"), IOStandard("SSTL12_DCI")),
Subsignal("ba", Pins("D33 B36"), IOStandard("SSTL12_DCI")), Subsignal("ba", Pins("D33 B36"), IOStandard("SSTL12_DCI")),
Subsignal("bg", Pins("C31 J30"), IOStandard("SSTL12_DCI")), Subsignal("bg", Pins("C31 J30"), IOStandard("SSTL12_DCI")),
Subsignal("cas_n", Pins("G32"), IOStandard("SSTL12_DCI")), Subsignal("ras_n", Pins("K30"), IOStandard("SSTL12_DCI")), # A16
Subsignal("cas_n", Pins("G32"), IOStandard("SSTL12_DCI")), # A15
Subsignal("we_n", Pins("A35"), IOStandard("SSTL12_DCI")), # A14
Subsignal("cke", Pins("G30"), IOStandard("SSTL12_DCI")), Subsignal("cke", Pins("G30"), IOStandard("SSTL12_DCI")),
Subsignal("clk_n", Pins("B34"), IOStandard("DIFF_SSTL12_DCI")), Subsignal("clk_n", Pins("B34"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("clk_p", Pins("C34"), IOStandard("DIFF_SSTL12_DCI")), Subsignal("clk_p", Pins("C34"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("cs_n", Pins("B35"), IOStandard("SSTL12_DCI")), Subsignal("cs_n", Pins("B35"), IOStandard("SSTL12_DCI")),
Subsignal("dm", Pins("E39 G37 N31 T30 L35 M34 J38 H33"), Subsignal("dm", Pins("R28 M27 H26 C29 G37 T30 M34 H33"),
IOStandard("POD12_DCI")), IOStandard("POD12_DCI")),
Subsignal("dq", Pins( Subsignal("dq", Pins(
"R25 P25 M25 L25 P26 R26 N27 N28", "R25 P25 M25 L25 P26 R26 N27 N28",
@ -178,18 +180,16 @@ _io = [
IOStandard("POD12_DCI"), IOStandard("POD12_DCI"),
Misc("PRE_EMPHASIS=RDRV_240"), Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")), Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dqs_n", Pins("M26 P28 J26 L28 D30 H27 A28 B29"), Subsignal("dqs_n", Pins("M26 J26 D30 A28 E40 M31 L36 H38"),
IOStandard("DIFF_POD12"), IOStandard("DIFF_POD12"),
Misc("PRE_EMPHASIS=RDRV_240"), Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")), Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dqs_p", Pins("N26 R28 J25 M27 D29 H26 A27 C29"), Subsignal("dqs_p", Pins("N26 J25 D29 A27 E39 N31 L35 J38"),
IOStandard("DIFF_POD12"), IOStandard("DIFF_POD12"),
Misc("PRE_EMPHASIS=RDRV_240"), Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")), Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("odt", Pins("E33"), IOStandard("SSTL12_DCI")), Subsignal("odt", Pins("E33"), IOStandard("SSTL12_DCI")),
Subsignal("ras_n", Pins("K30"), IOStandard("SSTL12_DCI")),
Subsignal("reset_n", Pins("D36"), IOStandard("LVCMOS12")), Subsignal("reset_n", Pins("D36"), IOStandard("LVCMOS12")),
Subsignal("we_n", Pins("A35"), IOStandard("SSTL12_DCI")),
Misc("SLEW=FAST") Misc("SLEW=FAST")
), ),
("ddram", 4, ("ddram", 4,
@ -200,12 +200,14 @@ _io = [
Subsignal("act_n", Pins("H13"), IOStandard("SSTL12_DCI")), Subsignal("act_n", Pins("H13"), IOStandard("SSTL12_DCI")),
Subsignal("ba", Pins("J15 H14"), IOStandard("SSTL12_DCI")), Subsignal("ba", Pins("J15 H14"), IOStandard("SSTL12_DCI")),
Subsignal("bg", Pins("D13 J13"), IOStandard("SSTL12_DCI")), Subsignal("bg", Pins("D13 J13"), IOStandard("SSTL12_DCI")),
Subsignal("cas_n", Pins("E15"), IOStandard("SSTL12_DCI")), Subsignal("ras_n", Pins("F15"), IOStandard("SSTL12_DCI")), # A16
Subsignal("cke", Pins("K13"), IOStandard("SSTL12_DCI")), Subsignal("cas_n", Pins("E15"), IOStandard("SSTL12_DCI")), # A15
Subsignal("cke", Pins("K13"), IOStandard("SSTL12_DCI")), # A14
Subsignal("we_n", Pins("D15"), IOStandard("SSTL12_DCI")),
Subsignal("clk_n", Pins("L13"), IOStandard("DIFF_SSTL12_DCI")), Subsignal("clk_n", Pins("L13"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("clk_p", Pins("L14"), IOStandard("DIFF_SSTL12_DCI")), Subsignal("clk_p", Pins("L14"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("cs_n", Pins("B16"), IOStandard("SSTL12_DCI")), Subsignal("cs_n", Pins("B16"), IOStandard("SSTL12_DCI")),
Subsignal("dm", Pins("A25 D24 C17 B19 F18 H19 F23 H23"), Subsignal("dm", Pins("N22 M22 K18 N17 D24 B19 H19 H23"),
IOStandard("POD12_DCI")), IOStandard("POD12_DCI")),
Subsignal("dq", Pins( Subsignal("dq", Pins(
"P24 N24 T24 R23 N23 P21 P23 R21", "P24 N24 T24 R23 N23 P21 P23 R21",
@ -219,18 +221,16 @@ _io = [
IOStandard("POD12_DCI"), IOStandard("POD12_DCI"),
Misc("PRE_EMPHASIS=RDRV_240"), Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")), Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dqs_n", Pins("R22 N21 H21 L22 K20 K17 P18 M17"), Subsignal("dqs_n", Pins("R22 H21 K20 P18 A24 B17 F17 E23"),
IOStandard("DIFF_POD12"), IOStandard("DIFF_POD12"),
Misc("PRE_EMPHASIS=RDRV_240"), Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")), Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dqs_p", Pins("T22 N22 J21 M22 L20 K18 P19 N17"), Subsignal("dqs_p", Pins("T22 J21 L20 P19 A25 C17 F18 F23"),
IOStandard("DIFF_POD12"), IOStandard("DIFF_POD12"),
Misc("PRE_EMPHASIS=RDRV_240"), Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")), Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("odt", Pins("C16"), IOStandard("SSTL12_DCI")), Subsignal("odt", Pins("C16"), IOStandard("SSTL12_DCI")),
Subsignal("ras_n", Pins("F15"), IOStandard("SSTL12_DCI")),
Subsignal("reset_n", Pins("D21"), IOStandard("LVCMOS12")), Subsignal("reset_n", Pins("D21"), IOStandard("LVCMOS12")),
Subsignal("we_n", Pins("D15"), IOStandard("SSTL12_DCI")),
Misc("SLEW=FAST") Misc("SLEW=FAST")
), ),
] ]