butterstick: add --sdram-device option
Set 64M16 as default sdram-device. Related to #298
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@ -28,7 +28,7 @@ from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT41K256M16
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from litedram.modules import MT41K64M16,MT41K128M16,MT41K256M16,MT41K512M16
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from litedram.phy import ECP5DDRPHY
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from litedram.phy import ECP5DDRPHY
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from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
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from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
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@ -84,8 +84,9 @@ class _CRG(Module):
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# BaseSoC ------------------------------------------------------------------------------------------
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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class BaseSoC(SoCCore):
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def __init__(self, revision="1.0", device="85F", sys_clk_freq=int(60e6), toolchain="trellis",
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def __init__(self, revision="1.0", device="85F", sdram_device="MT41K64M16", sys_clk_freq=int(60e6),
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with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
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toolchain="trellis", with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50",
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eth_dynamic_ip=False,
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with_spi_flash=False,
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with_spi_flash=False,
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with_led_chaser=True,
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with_led_chaser=True,
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**kwargs) :
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**kwargs) :
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@ -104,6 +105,14 @@ class BaseSoC(SoCCore):
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# DDR3 SDRAM -------------------------------------------------------------------------------
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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if not self.integrated_main_ram_size:
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available_sdram_modules = {
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"MT41K64M16": MT41K64M16,
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"MT41K128M16": MT41K128M16,
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"MT41K256M16": MT41K256M16,
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"MT41K512M16": MT41K512M16,
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}
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sdram_module = available_sdram_modules.get(sdram_device)
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self.submodules.ddrphy = ECP5DDRPHY(
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self.submodules.ddrphy = ECP5DDRPHY(
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platform.request("ddram"),
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platform.request("ddram"),
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sys_clk_freq=sys_clk_freq)
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sys_clk_freq=sys_clk_freq)
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@ -111,7 +120,7 @@ class BaseSoC(SoCCore):
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self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
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self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
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self.add_sdram("sdram",
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self.add_sdram("sdram",
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phy = self.ddrphy,
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phy = self.ddrphy,
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module = MT41K256M16(sys_clk_freq, "1:2"),
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module = sdram_module(sys_clk_freq, "1:2"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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)
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@ -148,6 +157,7 @@ def main():
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parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)")
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parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)")
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parser.add_argument("--revision", default="1.0", help="Board Revision: 1.0 (default)")
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parser.add_argument("--revision", default="1.0", help="Board Revision: 1.0 (default)")
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parser.add_argument("--device", default="85F", help="ECP5 device (default: 85F)")
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parser.add_argument("--device", default="85F", help="ECP5 device (default: 85F)")
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parser.add_argument("--sdram-device", default="MT41K64M16", help="SDRAM device (default: MT41K64M16)")
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ethopts = parser.add_mutually_exclusive_group()
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ethopts = parser.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Add Ethernet")
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ethopts.add_argument("--with-ethernet", action="store_true", help="Add Ethernet")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Add EtherBone")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Add EtherBone")
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