trenz_max1000: Review/Cleanup.
This commit is contained in:
Florent Kermarrec
parent
8ef138eaa0
commit
caac75c7db
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@ -1,8 +1,10 @@
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# This file is Copyright (c) 2019 (year 0 AG) Antti Lukats <antti.lukats@gmail.com>
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# This file is Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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# info about the board http://trenz.org/max1000-info
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2019-2021 Antti Lukats <antti.lukats@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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#
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# http://trenz.org/max1000-info
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from litex.build.generic_platform import *
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from litex.build.altera import AlteraPlatform
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@ -11,17 +13,30 @@ from litex.build.altera.programmer import USBBlaster
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("clk12", 0, Pins("H6"), IOStandard("3.3-V LVTTL")), # 12MHz clock
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("user_led", 0, Pins("C5"), IOStandard("3.3-V LVTTL")), # CONF Done, inverted polarity
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# Clk / Rst
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("clk12", 0, Pins("H6"), IOStandard("3.3-V LVTTL")),
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("sw", 0, Pins("E6"), IOStandard("3.3-V LVTTL")),
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("sw", 1, Pins("E7"), IOStandard("3.3-V LVTTL")), # nConfig
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# Leds
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("user_led", 0, Pins("A8"), IOStandard("3.3-V LVTTL")),
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("user_led", 1, Pins("A9"), IOStandard("3.3-V LVTTL")),
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("user_led", 2, Pins("A11"), IOStandard("3.3-V LVTTL")),
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("user_led", 3, Pins("A10"), IOStandard("3.3-V LVTTL")),
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("user_led", 4, Pins("B10"), IOStandard("3.3-V LVTTL")),
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("user_led", 5, Pins("C9"), IOStandard("3.3-V LVTTL")),
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("user_led", 6, Pins("C10"), IOStandard("3.3-V LVTTL")),
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("user_led", 7, Pins("D8"), IOStandard("3.3-V LVTTL")),
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# Buttons
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("user_btn", 0, Pins("E6"), IOStandard("3.3-V LVTTL")),
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("user_btn", 1, Pins("E7"), IOStandard("3.3-V LVTTL")), # nConfig.
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("B4"), IOStandard("3.3-V LVTTL")),
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Subsignal("rx", Pins("A4"), IOStandard("3.3-V LVTTL"))
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),
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# SPI Flash
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("B3")),
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Subsignal("clk", Pins("A3")),
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@ -38,26 +53,25 @@ _io = [
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IOStandard("3.3-V LVTTL"),
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),
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# SDRAM
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("sdram_clock", 0, Pins("M9"), IOStandard("3.3-V LVTTL")),
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("sdram", 0,
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Subsignal("a", Pins("K6 M5 N5 J8 N10 M11 N9 L10 M13 N8 N4 M10")), #0, 1, ...
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Subsignal("ba", Pins("N6 K8")),
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Subsignal("cs_n", Pins("M4")),
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Subsignal("cke", Pins("M8")),
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Subsignal("a", Pins(
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"K6 M5 N5 J8 N10 M11 N9 L10",
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"M13 N8 N4 M10")),
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Subsignal("ba", Pins("N6 K8")),
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Subsignal("cs_n", Pins("M4")),
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Subsignal("cke", Pins("M8")),
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Subsignal("ras_n", Pins("M7")),
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Subsignal("cas_n", Pins("N7")),
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Subsignal("we_n", Pins("K7")),
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Subsignal("dq", Pins("D11 G10 F10 F9 E10 D9 G9 F8 F13 E12 E13 D12 C12 B12 B13 A12")),
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Subsignal("we_n", Pins("K7")),
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Subsignal("dq", Pins(
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"D11 G10 F10 F9 E10 D9 G9 F8",
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"F13 E12 E13 D12 C12 B12 B13 A12")),
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Subsignal("dm", Pins("E9 F12")),
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IOStandard("3.3-V LVTTL")
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),
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("gpio_leds", 0,
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Pins("A8 A9 A11 A10 B10 C9 C10 D8"),
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IOStandard("3.3-V LVTTL")
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),
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# all IO not connected to peripherals mapped to MFIO
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# <- LEDS -> <- PMOD -> <- D0..D14, D11R, D12R -> <- AIN0..AIN7 -> JE [C O I S i1 i2]sw
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("bbio", 0, Pins("A8 A9 A11 A10 B10 C9 C10 D8 M3 L3 M2 M1 N3 N2 K2 K1 H8 K10 H5 H4 J1 J2 L12 J12 J13 K11 K12 J10 H10 H13 G12 B11 G13 E1 C2 C1 D1 E3 F1 E4 B1 E5 J6 J7 K5 L5 J5 L4 E6"),
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@ -69,11 +83,9 @@ _io = [
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# Platform -----------------------------------------------------------------------------------------
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class Platform(AlteraPlatform):
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default_clk_name = "clk12"
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default_clk_period = 83
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default_clk_name = "clk12"
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default_clk_period = 1e9/12e6
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# def __init__(self, device):
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# AlteraPlatform.__init__(self, device, _io)
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def __init__(self):
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AlteraPlatform.__init__(self, "10M08SAU169C8G", _io)
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self.add_platform_command("set_global_assignment -name FAMILY \"MAX 10\"")
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@ -3,7 +3,7 @@
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Jakub Cabal <jakubcabal@gmail.com>
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# Copyright (c) 2019-2021 Antti Lukats <antti.lukats@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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@ -11,7 +11,7 @@ import argparse
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from migen import *
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from litex_boards.platforms import trenz_max1000
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from litex_boards.platforms import max1000
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from litex.soc.cores.clock import CycloneVPLL
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from litex.soc.integration.soc_core import *
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@ -48,7 +48,7 @@ class _CRG(Module):
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), **kwargs):
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platform = trenz_max1000.Platform()
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platform = max1000.Platform()
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kwargs["integrated_rom_size"] = 0x6000
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kwargs["integrated_sram_size"] = 0x1000
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