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https://github.com/litex-hub/litex-boards.git
synced 2025-01-03 03:43:36 -05:00
targets/ulx3s and colorlight_5a_75b: cleanup USB ACM addition and only keep USB ACM changes.
- remove update in loading/flashing: we need to thinks how to integrate this. - remove specific README: documentation is moved to the files, link to more complete project can be added if maintained externally, as done for the iCEBreaker for example. - revert default freq on ULX3S to 50MHz and instantiate a second PLL as done on the colorlight.
This commit is contained in:
Florent Kermarrec
parent
4b4f2f9eb8
commit
cb95962850
5 changed files with 25 additions and 228 deletions
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@ -1,26 +0,0 @@
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USB
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===
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USB support has been integrated for the V7.0 this board. Supporting other
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versions should be trivial and just need pinning changes. To build with
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usb support just do;
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./colourlight_5a_75b.py --uart-name=usb_cdc
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To install onto the board;
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./colourlight_5a_75b.py --load
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The USB Serial connection will appear as /dev/ttyACMx, or equivalent on your OS.
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Pinning for V7.0;
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* Replace U23 with a SN74CBT3245APWR, or remove U23 and place jumper wires.
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(You're basically making the ports Bi-directional).
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* Place a 15K resistor between J4 pin 2 and J4 pin 4.
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* Place a 15K resistor between J4 pin 3 and J4 pin 4.
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* Place a 1.5K resistor between J4 pin 1 and J4 pin 3.
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* Connect USB DP (Green) to J4 pin 3, USB DN (White) to J4 pin 2.
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@ -1,11 +0,0 @@
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USB
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===
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USB support has been integrated and tested for V3.0.3 this board. Revisions
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higher than this should be supported. The USB connection is on US2.
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To build with usb support just do;
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./ulx3s.py --uart-name=usb_cdc
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The USB Serial connection will appear as /dev/ttyACMx, or equivalent on your OS.
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@ -1,149 +0,0 @@
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#!/usr/bin/env python3
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import sys
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import textwrap
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# Very basic bitstream to SVF converter, tested with the ULX3S WiFi interface
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flash_page_size = 256
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erase_block_size = 64*1024
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def bitreverse(x):
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y = 0
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for i in range(8):
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if (x >> (7 - i)) & 1 == 1:
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y |= (1 << i)
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return y
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with open(sys.argv[1], 'rb') as bitf:
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bs = bitf.read()
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# Autodetect IDCODE from bitstream
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idcode_cmd = bytes([0xE2, 0x00, 0x00, 0x00])
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idcode = None
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for i in range(len(bs) - 4):
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if bs[i:i+4] == idcode_cmd:
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idcode = bs[i+4] << 24
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idcode |= bs[i+5] << 16
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idcode |= bs[i+6] << 8
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idcode |= bs[i+7]
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break
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if idcode is None:
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print("Failed to find IDCODE in bitstream, check bitstream is valid")
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sys.exit(1)
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bitf.seek(0)
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address = 0
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last_page = -1
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with open(sys.argv[2], 'w') as svf:
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print("""
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STATE RESET;
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HDR 0;
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HIR 0;
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TDR 0;
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TIR 0;
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ENDDR DRPAUSE;
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ENDIR IRPAUSE;
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STATE IDLE;
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""", file=svf)
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print("""
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SIR 8 TDI (E0);
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SDR 32 TDI (00000000)
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TDO ({:08X})
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MASK (FFFFFFFF);
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""".format(idcode), file=svf)
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print("""
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SIR 8 TDI (1C);
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SDR 510 TDI (3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
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FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF);
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// Enter Programming mode
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SIR 8 TDI (C6);
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SDR 8 TDI (00);
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RUNTEST IDLE 2 TCK 1.00E-02 SEC;
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// Erase
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SIR 8 TDI (0E);
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SDR 8 TDI (01);
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RUNTEST IDLE 2 TCK 2.0E-1 SEC;
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// Read STATUS
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SIR 8 TDI (3C);
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SDR 32 TDI (00000000)
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TDO (00000000)
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MASK (0000B000);
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// Exit Programming mode
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SIR 8 TDI (26);
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RUNTEST IDLE 2 TCK 1.00E-02 SEC;
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// BYPASS
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SIR 8 TDI (FF);
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STATE IDLE;
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RUNTEST 32 TCK;
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RUNTEST 2.00E-2 SEC;
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// Enter SPI mode
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SIR 8 TDI (3A);
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SDR 16 TDI (68FE);
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STATE IDLE;
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RUNTEST 32 TCK;
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RUNTEST 2.00E-2 SEC;
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// SPI IO
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SDR 8 TDI (D5);
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RUNTEST 2.00E-0 SEC;
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// CONFIRM FLASH ID
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SDR 32 TDI (000000F9)
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TDO (68FFFFFF)
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MASK (FF000000);
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SDR 8 TDI(60);
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SDR 16 TDI(0080);
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RUNTEST 1.00E-0 SEC;
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""", file=svf)
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while True:
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if((address // 0x10000) != last_page):
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last_page = (address // 0x10000)
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print("""SDR 8 TDI (60);
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""", file=svf)
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address_flipped = [bitreverse(x) for x in [0xd8,int(address // 0x10000),0x00,0x00]]
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hex_address= ["{:02X}".format(x) for x in reversed(address_flipped)]
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print("\n".join(textwrap.wrap("SDR {} TDI ({});".format(8*len(hex_address), "".join(hex_address)), 100)), file=svf)
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print("""RUNTEST 3.00 SEC;
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""", file=svf)
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chunk = bitf.read(flash_page_size)
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if not chunk:
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break
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# Convert chunk to bit-reversed hex
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br_chunk = [bitreverse(x) for x in bytes([0x02, int(address / 0x10000 % 0x100),int(address / 0x100 % 0x100),int(address % 0x100)]) + chunk]
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address += len(chunk)
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hex_chunk = ["{:02X}".format(x) for x in reversed(br_chunk)]
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print("""
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SDR 8 TDI (60);
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""", file=svf)
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print("\n".join(textwrap.wrap("SDR {} TDI ({});".format(8*len(br_chunk), "".join(hex_chunk)), 100)), file=svf)
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print("""
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RUNTEST 2.50E-2 SEC;
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""", file=svf)
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print("""
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// BYPASS
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SIR 8 TDI (FF);
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//REFRESH
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SIR 8 TDI(79);
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SDR 24 TDI(000000);
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STATE IDLE;
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RUNTEST 32 TCK;
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RUNTEST 2.00E-2 SEC;
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STATE RESET;
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""", file=svf)
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@ -20,6 +20,16 @@
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# wishbone-tool --ethernet-host 192.168.1.50 --server terminal --csr-csv csr.csv
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# You should see the LiteX BIOS and be able to interact with it.
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#
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# 3) SoC with USB-ACM UART (on V7.0):
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# - Replace U23 with a SN74CBT3245APWR or remove U23 and place jumper wires to make the ports bi-directional.
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# - Place a 15K resistor between J4 pin 2 and J4 pin 4.
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# - Place a 15K resistor between J4 pin 3 and J4 pin 4.
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# - Place a 1.5K resistor between J4 pin 1 and J4 pin 3.
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# - Connect USB DP (Green) to J4 pin 3, USB DN (White) to J4 pin 2.
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# ./colorlight_5a_75b.py --revision=7.0 --uart-name=usb_cdcc
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# ./colorlight_5a_75b.py --load
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# You should see the LiteX BIOS and be able to interact with it.
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#
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# Disclaimer: SoC 2) is still a Proof of Concept with large timings violations on the IP/UDP and
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# Etherbone stack that need to be optimized. It was initially just used to validate the reversed
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# pinout but happens to work on hardware...
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@ -75,7 +85,6 @@ class _CRG(Module):
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self.clock_domains.cd_usb_48 = ClockDomain()
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usb_pll.create_clkout(self.cd_usb_12, 12e6, margin=0)
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usb_pll.create_clkout(self.cd_usb_48, 48e6, margin=0)
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#self.comb += self.cd_usb_48.clk.eq(self.cd_sys.clk)
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# SDRAM clock
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
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@ -127,44 +136,23 @@ class BaseSoC(SoCCore):
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# Load ---------------------------------------------------------------------------------------------
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def openocd_run_svf(filename, iface="ftdi"):
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def load():
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import os
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f = open("openocd.cfg", "w")
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if (iface == "ftdi"):
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f.write(
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"""adapter driver ftdi
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f.write(
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"""
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interface ftdi
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ftdi_vid_pid 0x0403 0x6011
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ftdi_channel 0
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ftdi_layout_init 0x0098 0x008b
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reset_config none
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adapter speed 25000
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adapter_khz 25000
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jtag newtap ecp5 tap -irlen 8 -expected-id 0x41111043
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""")
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elif (iface=="jlink"):
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f.write("""adapter driver jlink
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transport select jtag
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reset_config none
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telnet_port 4444
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adapter speed 10000
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jtag newtap lfe5u25 tap -irlen 8 -irmask 0xFF -ircapture 0x5 -expected-id 0x41111043
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""")
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else:
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print("Unrecognised jtag interface")
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exit()
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f.close()
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os.system("openocd -d0 -f openocd.cfg -c \"transport select jtag; init; svf -tap lfe5u25.tap {} -quiet -progress; exit\"".format(filename))
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os.system("rm openocd.cfg")
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os.system("openocd -f openocd.cfg -c \"transport select jtag; init; svf soc_basesoc_colorlight_5a_75b/gateware/top.svf; exit\"")
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exit()
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def load(iface="ftdi"):
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openocd_run_svf("soc_basesoc_colorlight_5a_75b/gateware/top.svf",iface=iface)
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def flash(iface="ftdi"):
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import os
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os.system("./bit_to_flash.py soc_basesoc_colorlight_5a_75b/gateware/top.bit soc_basesoc_colorlight_5a_75b/gateware/top.svf.flash")
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openocd_run_svf("soc_basesoc_colorlight_5a_75b/gateware/top.svf.flash",iface=iface)
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# Build --------------------------------------------------------------------------------------------
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def main():
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@ -177,18 +165,11 @@ def main():
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parser.add_argument("--with-etherbone", action="store_true", help="enable Etherbone support")
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parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY 0 or 1 (default=0)")
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parser.add_argument("--load", action="store_true", help="load bitstream")
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parser.add_argument("--flash", action="store_true", help="flash bitstream")
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parser.add_argument("--iface", default="ftdi", help="loading jtag interface")
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parser.add_argument("--sys-clk-freq", default=60e6,
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help="system clock frequency (default=60MHz)")
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parser.add_argument("--sys-clk-freq", default=60e6, help="system clock frequency (default=60MHz)")
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args = parser.parse_args()
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if args.load:
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load(iface=args.iface)
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if args.flash:
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flash(iface=args.iface)
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load()
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assert not (args.with_ethernet and args.with_etherbone)
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soc = BaseSoC(revision=args.revision,
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@ -42,16 +42,18 @@ class _CRG(Module):
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self.submodules.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(rst)
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pll.register_clkin(clk25, 25e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, margin=0)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst)
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# USB PLL
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if with_usb_pll:
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self.submodules.usb_pll = usb_pll = ECP5PLL()
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usb_pll.register_clkin(clk25, 25e6)
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self.clock_domains.cd_usb_12 = ClockDomain()
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self.clock_domains.cd_usb_48 = ClockDomain()
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pll.create_clkout(self.cd_usb_12, 12e6, margin=0)
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self.comb += self.cd_usb_48.clk.eq(self.cd_sys.clk)
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usb_pll.create_clkout(self.cd_usb_12, 12e6, margin=0)
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usb_pll.create_clkout(self.cd_usb_48, 48e6, margin=0)
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# SDRAM clock
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
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@ -95,8 +97,8 @@ def main():
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help="gateware toolchain to use, trellis (default) or diamond")
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parser.add_argument("--device", dest="device", default="LFE5U-45F",
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help="FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F")
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parser.add_argument("--sys-clk-freq", default=48e6,
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help="system clock frequency (default=48MHz)")
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parser.add_argument("--sys-clk-freq", default=50e6,
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help="system clock frequency (default=50MHz)")
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parser.add_argument("--sdram-module", default="MT48LC16M16",
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help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)")
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builder_args(parser)
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