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tang_nano_9k: Fix HyperRAM integration.

This commit is contained in:
Florent Kermarrec 2022-01-24 18:35:12 +01:00
parent 787f44e7d9
commit cc1b46f106
1 changed files with 22 additions and 22 deletions
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12
litex_boards/targets/sipeed_tang_nano_9k.py
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@ -76,7 +76,9 @@ class BaseSoC(SoCCore):
) )
self.cpu.set_reset_address(self.bus.regions["rom"].origin) self.cpu.set_reset_address(self.bus.regions["rom"].origin)
# HyperRam --------------------------------------------------------------------------------- # HyperRAM ---------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
# TODO: Use second 32Mbit PSRAM chip.
dq = platform.request("IO_psram_dq") dq = platform.request("IO_psram_dq")
rwds = platform.request("IO_psram_rwds") rwds = platform.request("IO_psram_rwds")
reset_n = platform.request("O_psram_reset_n") reset_n = platform.request("O_psram_reset_n")
@ -93,11 +95,9 @@ class BaseSoC(SoCCore):
hyperram_pads = HyperRAMPads(0) hyperram_pads = HyperRAMPads(0)
self.comb += ck[0].eq(hyperram_pads.clk) self.comb += ck[0].eq(hyperram_pads.clk)
self.comb += ck_n[0].eq(~hyperram0_pads.clk) self.comb += ck_n[0].eq(~hyperram_pads.clk)
self.submodules.hyperram0 = HyperRAM(hyperram_pads) self.submodules.hyperram = HyperRAM(hyperram_pads)
self.bus.add_slave("main_ram", slave=self.hyperram.bus, self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=self.mem_map["main_ram"], size=4*mB))
region=SoCRegion(origin=self.mem_map["main_ram"], size=4*mB))
# TODO: utilize another 32Mbit PSRAM chip
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
if with_led_chaser: if with_led_chaser: