tang_nano_9k: Fix HyperRAM integration.
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@ -76,28 +76,28 @@ class BaseSoC(SoCCore):
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)
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self.cpu.set_reset_address(self.bus.regions["rom"].origin)
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# HyperRam ---------------------------------------------------------------------------------
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dq = platform.request("IO_psram_dq")
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rwds = platform.request("IO_psram_rwds")
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reset_n = platform.request("O_psram_reset_n")
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cs_n = platform.request("O_psram_cs_n")
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ck = platform.request("O_psram_ck")
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ck_n = platform.request("O_psram_ck_n")
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class HyperRAMPads:
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def __init__(self, n):
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self.clk = Signal()
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self.rst_n = reset_n[n]
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self.dq = dq[8*n:8*(n+1)]
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self.cs_n = cs_n[n]
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self.rwds = rwds[n]
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# HyperRAM ---------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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# TODO: Use second 32Mbit PSRAM chip.
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dq = platform.request("IO_psram_dq")
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rwds = platform.request("IO_psram_rwds")
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reset_n = platform.request("O_psram_reset_n")
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cs_n = platform.request("O_psram_cs_n")
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ck = platform.request("O_psram_ck")
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ck_n = platform.request("O_psram_ck_n")
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class HyperRAMPads:
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def __init__(self, n):
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self.clk = Signal()
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self.rst_n = reset_n[n]
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self.dq = dq[8*n:8*(n+1)]
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self.cs_n = cs_n[n]
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self.rwds = rwds[n]
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hyperram_pads = HyperRAMPads(0)
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self.comb += ck[0].eq(hyperram_pads.clk)
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self.comb += ck_n[0].eq(~hyperram0_pads.clk)
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self.submodules.hyperram0 = HyperRAM(hyperram_pads)
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self.bus.add_slave("main_ram", slave=self.hyperram.bus,
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region=SoCRegion(origin=self.mem_map["main_ram"], size=4*mB))
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# TODO: utilize another 32Mbit PSRAM chip
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hyperram_pads = HyperRAMPads(0)
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self.comb += ck[0].eq(hyperram_pads.clk)
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self.comb += ck_n[0].eq(~hyperram_pads.clk)
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self.submodules.hyperram = HyperRAM(hyperram_pads)
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self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=self.mem_map["main_ram"], size=4*mB))
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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