Merge branch 'master' into master
This commit is contained in:
enjoy-digital
GitHub
commit
cd527f0fcb
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from litex_boards.community.targets import ac701
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from litex_boards.community.targets import de10lite
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from litex_boards.community.targets import de1soc
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from litex_boards.community.targets import de2_115
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from litex_boards.community.targets import ecp5_evn
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#from litex_boards.community.targets import ac701
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#from litex_boards.community.targets import de10lite
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#from litex_boards.community.targets import de1soc
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#from litex_boards.community.targets import de2_115
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#from litex_boards.community.targets import ecp5_evn
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from litex_boards.official.targets import arty
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from litex_boards.official.targets import de0nano
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from litex_boards.official.targets import genesys2
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from litex_boards.official.targets import kc705
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from litex_boards.official.targets import kcu105
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from litex_boards.official.targets import minispartan6
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from litex_boards.official.targets import nexys4ddr
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from litex_boards.official.targets import nexys_video
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from litex_boards.official.targets import simple
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from litex_boards.official.targets import versa_ecp5
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#from litex_boards.official.targets import arty
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#from litex_boards.official.targets import de0nano
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#from litex_boards.official.targets import genesys2
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#from litex_boards.official.targets import kc705
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#from litex_boards.official.targets import kcu105
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#from litex_boards.official.targets import minispartan6
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#from litex_boards.official.targets import nexys4ddr
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#from litex_boards.official.targets import nexys_video
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#from litex_boards.official.targets import simple
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#from litex_boards.official.targets import versa_ecp5
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from litex_boards.partner.targets import aller
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from litex_boards.partner.targets import nereid
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from litex_boards.partner.targets import netv2
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from litex_boards.partner.targets import tagus
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from litex_boards.partner.targets import trellisboard
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from litex_boards.partner.targets import ulx3s
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#from litex_boards.partner.targets import aller
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#from litex_boards.partner.targets import nereid
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#from litex_boards.partner.targets import netv2
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#from litex_boards.partner.targets import tagus
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#from litex_boards.partner.targets import trellisboard
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#from litex_boards.partner.targets import ulx3s
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@ -0,0 +1,246 @@
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#!/usr/bin/env python3
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# This file is Copyright (c) 2019 Sean Cross <sean@xobs.io>
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# This file is Copyright (c) 2018 David Shah <dave@ds0.me>
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# License: BSD
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.soc.cores import up5kspram
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from litex.soc.integration import SoCCore
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from litex.soc.integration.builder import Builder, builder_argdict, builder_args
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from litex.soc.integration.soc_core import soc_core_argdict, soc_core_args
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from valentyusb.usbcore import io as usbio
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from valentyusb.usbcore.cpu import dummyusb, epfifo
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import os, shutil, subprocess
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform):
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clk48_raw = platform.request("clk48")
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clk12 = Signal()
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reset_delay = Signal(12, reset=4095)
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self.clock_domains.cd_por = ClockDomain()
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self.reset = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_usb_12 = ClockDomain()
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self.clock_domains.cd_usb_48 = ClockDomain()
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platform.add_period_constraint(self.cd_usb_48.clk, 1e9/48e6)
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platform.add_period_constraint(self.cd_sys.clk, 1e9/12e6)
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platform.add_period_constraint(self.cd_usb_12.clk, 1e9/12e6)
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platform.add_period_constraint(clk48_raw, 1e9/48e6)
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# POR reset logic- POR generated from sys clk, POR logic feeds sys clk
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# reset.
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self.comb += [
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self.cd_por.clk.eq(self.cd_sys.clk),
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self.cd_sys.rst.eq(reset_delay != 0),
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self.cd_usb_12.rst.eq(reset_delay != 0),
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]
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# POR reset logic- POR generated from sys clk, POR logic feeds sys clk
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# reset.
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self.comb += [
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self.cd_usb_48.rst.eq(reset_delay != 0),
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]
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self.comb += self.cd_usb_48.clk.eq(clk48_raw)
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self.specials += Instance(
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"SB_PLL40_CORE",
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# Parameters
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p_DIVR = 0,
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p_DIVF = 15,
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p_DIVQ = 5,
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p_FILTER_RANGE = 1,
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p_FEEDBACK_PATH = "SIMPLE",
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p_DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED",
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p_FDA_FEEDBACK = 15,
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p_DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED",
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p_FDA_RELATIVE = 0,
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p_SHIFTREG_DIV_MODE = 1,
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p_PLLOUT_SELECT = "GENCLK_HALF",
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p_ENABLE_ICEGATE = 0,
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# IO
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i_REFERENCECLK = clk48_raw,
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o_PLLOUTCORE = clk12,
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# o_PLLOUTGLOBAL = clk12,
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#i_EXTFEEDBACK,
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#i_DYNAMICDELAY,
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#o_LOCK,
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i_BYPASS = 0,
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i_RESETB = 1,
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#i_LATCHINPUTVALUE,
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#o_SDO,
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#i_SDI,
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)
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self.comb += self.cd_sys.clk.eq(clk12)
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self.comb += self.cd_usb_12.clk.eq(clk12)
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self.sync.por += \
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If(reset_delay != 0,
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reset_delay.eq(reset_delay - 1)
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)
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self.specials += AsyncResetSynchronizer(self.cd_por, self.reset)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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"""A SoC on Fomu, optionally with a softcore CPU"""
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# Create a default CSR map to prevent values from getting reassigned.
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# This increases consistency across litex versions.
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SoCCore.csr_map = {
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"ctrl": 0, # provided by default (optional)
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"crg": 1, # user
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"uart_phy": 2, # provided by default (optional)
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"uart": 3, # provided by default (optional)
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"identifier_mem": 4, # provided by default (optional)
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"timer0": 5, # provided by default (optional)
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"cpu_or_bridge": 8,
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"usb": 9,
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"picorvspi": 10,
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"touch": 11,
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"reboot": 12,
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"rgb": 13,
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"version": 14,
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}
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# Statically-define the memory map, to prevent it from shifting across
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# various litex versions.
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SoCCore.mem_map = {
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"rom": 0x00000000, # (default shadow @0x80000000)
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"sram": 0x10000000, # (default shadow @0xa0000000)
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"spiflash": 0x20000000, # (default shadow @0xa0000000)
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"main_ram": 0x40000000, # (default shadow @0xc0000000)
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"csr": 0x60000000, # (default shadow @0xe0000000)
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}
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interrupt_map = {
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"usb": 3,
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}
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interrupt_map.update(SoCCore.interrupt_map)
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def __init__(self, board,
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pnr_placer=None, pnr_seed=0, usb_core="dummyusb", usb_bridge=False,
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**kwargs):
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"""Create a basic SoC for Fomu.
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Create a basic SoC for Fomu, including a 48 MHz and 12 MHz clock
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domain called `usb_48` and `usb_12`. The `sys` frequency will
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run at 12 MHz.
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The USB core will optionally have a bridge to the Wishbone bus.
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Args:
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board (str): Which Fomu board to build for: pvt, evt, or hacker
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pnr_placer (str): Which placer to use in nextpnr
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pnr_seed (int): Which seed to use in nextpnr
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usb_core (str): The name of the USB core to use, if any: dummyusb, epfifo
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usb_bridge (bool): Whether to include a USB-to-Wishbone bridge
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Raises:
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ValueError: If either the `usb_core` or `board` are unrecognized
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Returns:
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Newly-constructed SoC
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"""
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if board == "pvt":
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from litex_boards.partner.platforms.fomu_pvt import Platform
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elif board == "hacker":
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from litex_boards.partner.platforms.fomu_hacker import Platform
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elif board == "evt":
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from litex_boards.partner.platforms.fomu_evt import Platform
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else:
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raise ValueError("unrecognized fomu board: {}".format(board))
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platform = Platform()
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clk_freq = int(12e6)
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SoCCore.__init__(self, platform, clk_freq,
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cpu_type=None,
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cpu_variant=None,
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integrated_sram_size=0,
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with_uart=False,
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with_ctrl=False,
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**kwargs)
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self.submodules.crg = _CRG(platform)
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# UP5K has single port RAM, which is a dedicated 128 kilobyte block.
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# Use this as CPU RAM.
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spram_size = 128*1024
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self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
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self.register_mem("sram", 0x10000000, self.spram.bus, spram_size)
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if usb_core is not None:
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# Add USB pads. We use DummyUsb, which simply enumerates as a USB
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# device. Then all interaction is done via the wishbone bridge.
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usb_pads = platform.request("usb")
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usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
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if usb_core == "dummyusb":
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self.submodules.usb = dummyusb.DummyUsb(usb_iobuf, debug=usb_bridge)
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elif usb_core == "epfifo":
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self.submodules.usb = epfifo.PerEndpointFifo(usb_iobuf, debug=usb_bridge)
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else:
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raise ValueError("unrecognized usb_core: {}".args(usb_core))
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if usb_bridge:
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self.add_wb_master(self.usb.debug_bridge.wishbone)
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# Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command.
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# "-reult" adds an additional LUT pass to pack more stuff in, and
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# "-dffe_min_ce_use 4" flag prevents Yosys from generating a
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# Clock Enable signal for a LUT that has fewer than 4 flip-flops.
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# This increases density, and lets us use the FPGA more efficiently.
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platform.toolchain.nextpnr_yosys_template[2] += " -relut -dffe_min_ce_use 4"
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# Allow us to set the nextpnr seed, because some values don't meet timing.
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platform.toolchain.nextpnr_build_template[1] += " --seed " + str(pnr_seed)
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# Different placers can improve packing efficiency, however not all placers
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# are enabled on all builds of nextpnr-ice40. Let the user override which
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# placer they want to use.
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if pnr_placer is not None:
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platform.toolchain.nextpnr_build_template[1] += " --placer {}".format(pnr_placer)
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# Build --------------------------------------------------------------------------------------------
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def add_dfu_suffix(fn):
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fn_base, _ext = os.path.splitext(fn)
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fn_dfu = fn_base + '.dfu'
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shutil.copyfile(fn, fn_dfu)
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subprocess.check_call(['dfu-suffix', '--pid', '1209', '--vid', '5bf0', '--add', fn_dfu])
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Fomu")
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parser.add_argument(
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"--board", choices=["evt", "pvt", "hacker"], required=True,
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help="build for a particular hardware board"
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)
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parser.add_argument(
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"--seed", default=0, help="seed to use in nextpnr"
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)
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parser.add_argument(
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"--placer", default="heap", choices=["sa", "heap"], help="which placer to use in nextpnr"
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)
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(board=args.board, pnr_placer=args.placer, pnr_seed=args.seed,
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debug=True, **soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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