add digilent basys3 support
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helium729
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020-2021 Xuanyu Hu <xuanyu.hu@whu.edu.cn>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk100", 0, Pins("W3"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("U16"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("E19"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("U19"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("V19"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("W18"), IOStandard("LVCMOS33")),
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("user_led", 5, Pins("U15"), IOStandard("LVCMOS33")),
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("user_led", 6, Pins("U14"), IOStandard("LVCMOS33")),
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("user_led", 7, Pins("V14"), IOStandard("LVCMOS33")),
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("user_led", 8, Pins("V13"), IOStandard("LVCMOS33")),
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("user_led", 9, Pins("V3"), IOStandard("LVCMOS33")),
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("user_led", 10, Pins("W3"), IOStandard("LVCMOS33")),
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("user_led", 11, Pins("U3"), IOStandard("LVCMOS33")),
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("user_led", 12, Pins("P3"), IOStandard("LVCMOS33")),
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("user_led", 13, Pins("N3"), IOStandard("LVCMOS33")),
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("user_led", 14, Pins("P1"), IOStandard("LVCMOS33")),
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("user_led", 15, Pins("L1"), IOStandard("LVCMOS33")),
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# Switches
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("user_sw", 0, Pins("V17"), IOStandard("LVCMOS33")),
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("user_sw", 1, Pins("V16"), IOStandard("LVCMOS33")),
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("user_sw", 2, Pins("W16"), IOStandard("LVCMOS33")),
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("user_sw", 3, Pins("W17"), IOStandard("LVCMOS33")),
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("user_sw", 4, Pins("W15"), IOStandard("LVCMOS33")),
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("user_sw", 5, Pins("V15"), IOStandard("LVCMOS33")),
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("user_sw", 6, Pins("W14"), IOStandard("LVCMOS33")),
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("user_sw", 7, Pins("W13"), IOStandard("LVCMOS33")),
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("user_sw", 8, Pins("V2"), IOStandard("LVCMOS33")),
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("user_sw", 9, Pins("T3"), IOStandard("LVCMOS33")),
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("user_sw", 10, Pins("T2"), IOStandard("LVCMOS33")),
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("user_sw", 11, Pins("R3"), IOStandard("LVCMOS33")),
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("user_sw", 12, Pins("W2"), IOStandard("LVCMOS33")),
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("user_sw", 13, Pins("U1"), IOStandard("LVCMOS33")),
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("user_sw", 14, Pins("T1"), IOStandard("LVCMOS33")),
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("user_sw", 15, Pins("R2"), IOStandard("LVCMOS33")),
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# Buttons
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("user_btnu", 0, Pins("T18"), IOStandard("LVCMOS33")),
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("user_btnd", 0, Pins("U17"), IOStandard("LVCMOS33")),
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("user_btnl", 0, Pins("W19"), IOStandard("LVCMOS33")),
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("user_btnr", 0, Pins("T17"), IOStandard("LVCMOS33")),
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("user_btnc", 0, Pins("U18"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("A18")),
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Subsignal("rx", Pins("B18")),
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IOStandard("LVCMOS33"),
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),
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# VGA
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("vga", 0,
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Subsignal("hsync_n", Pins("P19")),
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Subsignal("vsync_n", Pins("R18")),
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Subsignal("r", Pins("G19 H19 J19 N19")),
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Subsignal("g", Pins("J17 H17 G17 D17")),
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Subsignal("b", Pins("N18 L18 K18 J18")),
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IOStandard("LVCMOS33")
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),
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# USB PS/2
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("usbhost", 0,
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Subsignal("ps2_clk", Pins("B6")),
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Subsignal("ps2_data", Pins("A6")),
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IOStandard("LVCMOS33"))
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("pmoda", "J1 L2 J2 G2 H1 K2 H2 G3"),
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("pmodb", "A14 A16 B15 B16 A15 A17 C15 C16"),
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("pmodc", "K17 M18 N17 P18 L17 M19 P17 R18"),
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("pmodxdac", "J3 L3 M2 N2 K3 M3 M1 N1"),
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]
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# PMODS --------------------------------------------------------------------------------------------
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def sdcard_pmod_io(pmod):
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return [
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# SDCard PMOD:
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# - https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
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("spisdcard", 0,
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Subsignal("clk", Pins(f"{pmod}:3")),
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Subsignal("mosi", Pins(f"{pmod}:1"), Misc("PULLUP True")),
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Subsignal("cs_n", Pins(f"{pmod}:0"), Misc("PULLUP True")),
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Subsignal("miso", Pins(f"{pmod}:2"), Misc("PULLUP True")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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("sdcard", 0,
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Subsignal("data", Pins(f"{pmod}:2 {pmod}:4 {pmod}:5 {pmod}:0"), Misc("PULLUP True")),
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Subsignal("cmd", Pins(f"{pmod}:1"), Misc("PULLUP True")),
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Subsignal("clk", Pins(f"{pmod}:3")),
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Subsignal("cd", Pins(f"{pmod}:6")),
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Misc("SLEW=FAST"),
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IOStandard("LVCMOS33"),
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),
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]
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_sdcard_pmod_io = sdcard_pmod_io("pmoda") # SDCARD PMOD on JD.
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7a35t-CPG236-1", _io, _connectors, toolchain="vivado")
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def create_programmer(self):
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return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a35t.bit")
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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@ -0,0 +1,116 @@
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020-2021 Xuanyu Hu <xuanyu.hu@whu.edu.cn>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from litex.build.xilinx import platform
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from migen import *
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from litex_boards.platforms import basys3
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.video import VideoVGAPHY
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT47H64M16
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from litedram.phy import s7ddrphy
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from liteeth.phy.rmii import LiteEthPHYRMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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self.clock_domains.cd_vga = ClockDomain(reset_less=True)
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self.submodules.pll = pll = S7MMCM(speedgrade=-1)
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self.comb += pll.reset.eq(~platform.request("user_btnc") | self.rst)
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pll.register_clkin(platform.request("clk100"), 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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pll.create_clkout(self.cd_vga, 40e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(75e6), with_video_terminal=False, with_video_framebuffer=False, **kwargs):
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platform = basys3.Platform()
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# SoCCore ----------------------------------_-----------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Basys3",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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if with_video_terminal or with_video_framebuffer:
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self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Basys3")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)")
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sdopts = parser.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
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parser.add_argument("--sdcard-adapter", type=str, help="SDCard PMOD adapter: digilent (default) or numato")
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viopts = parser.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA)")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (VGA)")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_video_terminal = args.with_video_terminal,
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with_video_framebuffer = args.with_video_framebuffer,
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**soc_core_argdict(args)
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)
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soc.platform.add_extension(basys3._sdcard_pmod_io)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if __name__ == "__main__":
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main()
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@ -43,6 +43,7 @@ class TestTargets(unittest.TestCase):
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platforms.append("ac701")
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platforms.append("aller")
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platforms.append("arty")
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platforms.append("basys3")
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platforms.append("mimas_a7")
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platforms.append("netv2")
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platforms.append("nexys4ddr")
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