Added icebreaker platform and target.
Target is heavily based on Fomu.
This commit is contained in:
Piotr Esden-Tempski
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fd6c555117
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# This file is Copyright (c) 2020 Piotr Esden-Tempski <piotr@esden.net>
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# License: BSD
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# iCEBreaker FPGA:
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# - Crowd Supply campaign: https://www.crowdsupply.com/1bitsquared/icebreaker
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# - 1BitSquared Store: https://1bitsquared.com/products/icebreaker
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# - Design files: https://github.com/icebreaker/icebreaker
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice.programmer import IceStormProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("user_led_n", 0, Pins("11"), IOStandard("LVCMOS33")),
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("user_led_n", 1, Pins("37"), IOStandard("LVCMOS33")),
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# Color-specific aliases
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("user_ledr_n", 0, Pins("11"), IOStandard("LVCMOS33")),
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("user_ledg_n", 0, Pins("37"), IOStandard("LVCMOS33")),
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("user_btn_n", 0, Pins("10"), IOStandard("LVCMOS33")),
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("serial", 0,
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Subsignal("rx", Pins("6")),
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Subsignal("tx", Pins("9"), Misc("PULLUP")),
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IOStandard("LVCMOS33")
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),
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("spiflash", 0,
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Subsignal("cs_n", Pins("16"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("15"), IOStandard("LVCMOS33")),
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Subsignal("miso", Pins("17"), IOStandard("LVCMOS33")),
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Subsignal("mosi", Pins("14"), IOStandard("LVCMOS33")),
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Subsignal("wp", Pins("12"), IOStandard("LVCMOS33")),
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Subsignal("hold", Pins("13"), IOStandard("LVCMOS33")),
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("16"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("15"), IOStandard("LVCMOS33")),
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Subsignal("dq", Pins("14 17 12 13"), IOStandard("LVCMOS33")),
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),
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("clk12", 0, Pins("35"), IOStandard("LVCMOS33"))
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("PMOD1A", "4 2 47 45 3 48 46 44"),
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("PMOD1B", "43 38 34 31 42 36 32 28"),
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("PMOD2", "27 25 21 19 26 23 20 18")
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]
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# The attached LED/button section can be either used standalone or as a PMOD.
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# Attach to platform using:
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# plat.add_extension(break_off_pmod)
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# pmod_btn = plat.request("user_btn")
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break_off_pmod = [
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("user_btn", 0, Pins("PMOD2:6"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("PMOD2:3"), IOStandard("LVCMOS33")),
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("user_btn", 2, Pins("PMOD2:7"), IOStandard("LVCMOS33")),
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("user_led", 0, Pins("PMOD2:4"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("PMOD2:0"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("PMOD2:1"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("PMOD2:5"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("PMOD2:2"), IOStandard("LVCMOS33")),
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# Color-specific aliases
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("user_ledr", 0, Pins("PMOD2:4"), IOStandard("LVCMOS33")),
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("user_ledg", 0, Pins("PMOD2:0"), IOStandard("LVCMOS33")),
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("user_ledg", 1, Pins("PMOD2:1"), IOStandard("LVCMOS33")),
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("user_ledg", 2, Pins("PMOD2:5"), IOStandard("LVCMOS33")),
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("user_ledg", 3, Pins("PMOD2:2"), IOStandard("LVCMOS33"))
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk12"
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default_clk_period = 1e9 / 12e6
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def __init__(self):
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LatticePlatform.__init__(self, "ice40-up5k-sg48", _io, _connectors,
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toolchain="icestorm")
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def create_programmer(self):
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return IceStormProgrammer()
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#!/usr/bin/env python3
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# This file is Copyright (c) 2019 Sean Cross <sean@xobs.io>
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# This file is Copyright (c) 2018 David Shah <dave@ds0.me>
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# This file is Copyright (c) 2020 Piotr Esden-Tempski <piotr@esden.net>
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# License: BSD
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# This target was originally based on the Fomu target.
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.soc.cores import up5kspram
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.integration.builder import Builder, builder_argdict, builder_args
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from litex.soc.integration.soc_core import soc_core_argdict, soc_core_args
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from litex.soc.integration.doc import AutoDoc
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from litex_boards.partner.platforms.icebreaker import Platform
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import os, shutil, subprocess
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module, AutoDoc):
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"""Fomu Clock Resource Generator
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Fomu is a USB device, which means it must have a 12 MHz clock. Valentyusb
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oversamples the clock by 4x, which drives the requirement for a 48 MHz clock.
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The ICE40UP5k is a relatively low speed grade of FPGA that is incapable of
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running the entire design at 48 MHz, so the majority of the logic is placed
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in the 12 MHz domain while only critical USB logic is placed in the fast
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48 MHz domain.
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Fomu has a 48 MHz crystal on it, which provides the raw clock input. This
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signal is fed through the ICE40 PLL in order to divide it down into a 12 MHz
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signal and keep the clocks within 1ns of phase. Earlier designs used a simple
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flop, however this proved unreliable when the FPGA became very full.
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The following clock domains are available on this design:
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+---------+------------+---------------------------------+
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| Name | Frequency | Description |
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+=========+============+=================================+
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| usb_48 | 48 MHz | Raw USB signals and pulse logic |
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+---------+------------+---------------------------------+
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| usb_12 | 12 MHz | USB control logic |
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+---------+------------+---------------------------------+
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| sys | 12 MHz | System CPU and wishbone bus |
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+---------+------------+---------------------------------+
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"""
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def __init__(self, platform):
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pass
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# clk12 = platform.request("clk12")
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# clk12 = Signal()
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# reset_delay = Signal(12, reset=4095)
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# self.clock_domains.cd_por = ClockDomain()
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# self.reset = Signal()
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# self.clock_domains.cd_sys = ClockDomain()
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# self.clock_domains.cd_usb_12 = ClockDomain()
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# self.clock_domains.cd_usb_48 = ClockDomain()
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# platform.add_period_constraint(self.cd_usb_48.clk, 1e9/48e6)
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# platform.add_period_constraint(self.cd_sys.clk, 1e9/12e6)
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# platform.add_period_constraint(self.cd_usb_12.clk, 1e9/12e6)
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# platform.add_period_constraint(clk48_raw, 1e9/48e6)
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# # POR reset logic- POR generated from sys clk, POR logic feeds sys clk
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# # reset.
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# self.comb += [
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# self.cd_por.clk.eq(self.cd_sys.clk),
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# self.cd_sys.rst.eq(reset_delay != 0),
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# self.cd_usb_12.rst.eq(reset_delay != 0),
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# ]
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# # POR reset logic- POR generated from sys clk, POR logic feeds sys clk
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# # reset.
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# self.comb += [
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# self.cd_usb_48.rst.eq(reset_delay != 0),
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# ]
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# self.comb += self.cd_usb_48.clk.eq(clk48_raw)
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# self.specials += Instance(
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# "SB_PLL40_CORE",
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# # Parameters
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# p_DIVR = 0,
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# p_DIVF = 15,
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# p_DIVQ = 5,
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# p_FILTER_RANGE = 1,
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# p_FEEDBACK_PATH = "SIMPLE",
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# p_DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED",
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# p_FDA_FEEDBACK = 15,
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# p_DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED",
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# p_FDA_RELATIVE = 0,
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# p_SHIFTREG_DIV_MODE = 1,
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# p_PLLOUT_SELECT = "GENCLK_HALF",
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# p_ENABLE_ICEGATE = 0,
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# # IO
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# i_REFERENCECLK = clk48_raw,
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# o_PLLOUTCORE = clk12,
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# # o_PLLOUTGLOBAL = clk12,
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# #i_EXTFEEDBACK,
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# #i_DYNAMICDELAY,
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# #o_LOCK,
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# i_BYPASS = 0,
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# i_RESETB = 1,
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# #i_LATCHINPUTVALUE,
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# #o_SDO,
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# #i_SDI,
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# )
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# self.comb += self.cd_sys.clk.eq(clk12)
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# self.comb += self.cd_usb_12.clk.eq(clk12)
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# self.sync.por += \
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# If(reset_delay != 0,
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# reset_delay.eq(reset_delay - 1)
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# )
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# self.specials += AsyncResetSynchronizer(self.cd_por, self.reset)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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"""A SoC on iCEBreaker, optionally with a softcore CPU"""
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# Create a default CSR map to prevent values from getting reassigned.
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# This increases consistency across litex versions.
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SoCCore.csr_map = {
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"ctrl": 0, # provided by default (optional)
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"crg": 1, # user
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"uart_phy": 2, # provided by default (optional)
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"uart": 3, # provided by default (optional)
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"identifier_mem": 4, # provided by default (optional)
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"timer0": 5, # provided by default (optional)
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"cpu_or_bridge": 8,
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"usb": 9,
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"picorvspi": 10,
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"touch": 11,
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"reboot": 12,
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"rgb": 13,
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"version": 14,
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}
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# Statically-define the memory map, to prevent it from shifting across
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# various litex versions.
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SoCCore.mem_map = {
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"rom": 0x00000000, # (default shadow @0x80000000)
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"sram": 0x10000000, # (default shadow @0xa0000000)
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"spiflash": 0x20000000, # (default shadow @0xa0000000)
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"main_ram": 0x40000000, # (default shadow @0xc0000000)
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"csr": 0xe0000000, # (default shadow @0x60000000)
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}
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def __init__(self,
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pnr_placer="heap", pnr_seed=0, usb_core="dummyusb", usb_bridge=False,
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**kwargs):
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"""Create a basic SoC for iCEBraker.
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Create a basic SoC for iCEBraker. The `sys` frequency will run at 12 MHz.
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Args:
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pnr_placer (str): Which placer to use in nextpnr
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pnr_seed (int): Which seed to use in nextpnr
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Returns:
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Newly-constructed SoC
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"""
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platform = Platform()
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if "cpu_type" not in kwargs:
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kwargs["cpu_type"] = None
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kwargs["cpu_variant"] = None
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clk_freq = int(12e6)
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kwargs["integrated_sram_size"] = 0
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SoCCore.__init__(self, platform, clk_freq,
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with_uart=True,
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with_ctrl=True,
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**kwargs)
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self.submodules.crg = _CRG(platform)
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# UP5K has single port RAM, which is a dedicated 128 kilobyte block.
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# Use this as CPU RAM.
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spram_size = 128 * 1024
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self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
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self.register_mem("sram", self.mem_map["sram"], self.spram.bus, spram_size)
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# Override default LiteX's yosys/build templates
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assert hasattr(platform.toolchain, "yosys_template")
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assert hasattr(platform.toolchain, "build_template")
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platform.toolchain.yosys_template = [
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"{read_files}",
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"attrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0",
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"synth_ice40 -json {build_name}.json -top {build_name}",
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]
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platform.toolchain.build_template = [
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"yosys -q -l {build_name}.rpt {build_name}.ys",
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"nextpnr-ice40 --json {build_name}.json --pcf {build_name}.pcf --asc {build_name}.txt \
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--pre-pack {build_name}_pre_pack.py --{architecture} --package {package}",
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"icepack {build_name}.txt {build_name}.bin"
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]
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# Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command.
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# The "-reult" adds an additional LUT pass to pack more stuff in,
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# and the "-dffe_min_ce_use 4" flag prevents Yosys from generating a
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# Clock Enable signal for a LUT that has fewer than 4 flip-flops.
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# This increases density, and lets us use the FPGA more efficiently.
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platform.toolchain.yosys_template[2] += " -relut -abc2 -dffe_min_ce_use 4 -relut"
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#if use_dsp:
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# platform.toolchain.yosys_template[2] += " -dsp"
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# Disable final deep-sleep power down so firmware words are loaded
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# onto softcore's address bus.
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platform.toolchain.build_template[2] = "icepack -s {build_name}.txt {build_name}.bin"
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# Allow us to set the nextpnr seed
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platform.toolchain.build_template[1] += " --seed " + str(pnr_seed)
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if pnr_placer is not None:
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platform.toolchain.build_template[1] += " --placer {}".format(pnr_placer)
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# Build --------------------------------------------------------------------------------------------
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def add_dfu_suffix(fn):
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fn_base, _ext = os.path.splitext(fn)
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fn_dfu = fn_base + '.dfu'
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shutil.copyfile(fn, fn_dfu)
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subprocess.check_call(['dfu-suffix', '--pid', '1209', '--vid', '5bf0', '--add', fn_dfu])
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
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parser.add_argument(
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"--seed", default=0, help="seed to use in nextpnr"
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)
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parser.add_argument(
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"--placer", default="heap", choices=["sa", "heap"], help="which placer to use in nextpnr"
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)
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(pnr_placer=args.placer, pnr_seed=args.seed,
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debug=True, **soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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