Add HPC Store XC7K420T board
This commit is contained in:
Hans Baier
parent
45494f60e0
commit
d1096a2cd0
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.build.openocd import OpenOCD
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# Board support for this chinese Kintex 420T board by "HPC FPGA Board Store"
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# https://www.aliexpress.com/item/1005001631827738.html
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk100", 0, Pins("U24"), IOStandard("LVCMOS33")),
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("diffclk100", 0,
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Subsignal("p", Pins("U22"), IOStandard("LVDS_25")),
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Subsignal("n", Pins("U23"), IOStandard("LVDS_25"))
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),
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# Leds
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("user_led_n", 0, Pins("A27"), IOStandard("LVCMOS15")),
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("user_led_n", 1, Pins("E24"), IOStandard("LVCMOS15")),
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("user_led_n", 2, Pins("G24"), IOStandard("LVCMOS15")),
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("user_led_n", 3, Pins("H21"), IOStandard("LVCMOS15")),
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("user_led_n", 4, Pins("G27"), IOStandard("LVCMOS15")),
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("user_led_n", 5, Pins("H26"), IOStandard("LVCMOS15")),
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("user_led_n", 6, Pins("H25"), IOStandard("LVCMOS15")),
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("user_led_n", 7, Pins("H24"), IOStandard("LVCMOS15")),
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# Buttons
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("user_btn_n", 0, Pins("Y23"), IOStandard("LVCMOS15")),
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("user_btn_n", 1, Pins("J24"), IOStandard("LVCMOS15")), # J4 jumper 2.5V or 3.3V
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# I2C / AT24C04
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("i2c", 0,
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Subsignal("scl", Pins("C17")),
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Subsignal("sda", Pins("C16")),
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IOStandard("LVCMOS33")
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),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("D16")), # CH340_TX
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Subsignal("rx", Pins("D17")), # CH340_RX
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IOStandard("LVCMOS33")
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),
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# DDR3 SDRAM near SFP ports
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("ddram", 0,
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Subsignal("a", Pins(
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"F28 E29 F26 D29 B29 C30 A30 B28 C29 B30 E30 E26 A28 H29 F25"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("F30 G28 E28"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("H27"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("G30"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("G29"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("H30"), IOStandard("SSTL15")),
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Subsignal("dm", Pins(
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"B22 E19 F22 K19 M23 P18 P26 N29"),
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IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"A21 A22 A23 B23 B19 C19 A20 B20 C21 D21 C22 D22 E18 D18 E20 E21" + \
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"G18 F18 G20 F20 H20 G22 G23 F23 L18 J18 J19 K20 J22 H22 K23 J23" + \
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"N24 N22 P24 P23 L20 M22 M24 N25 M17 N19 N17 P17 N20 N21 P21 P19" + \
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"K26 K25 L26 L25 M25 N26 P28 P27 L30 M29 P29 R29 K28 K29 K30 M28"),
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IOStandard("SSTL15_T_DCI")),
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Subsignal("dqs_p", Pins("B18 E23 H19 K21 L23 M18 N27 N30"),
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IOStandard("DIFF_SSTL15")),
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Subsignal("dqs_n", Pins("A18 D23 G19 J21 K24 M19 M27 M30"),
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IOStandard("DIFF_SSTL15")),
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Subsignal("clk_p", Pins("J26"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("J27"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("G25"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("J28"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("F27"), IOStandard("LVCMOS15")),
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Misc("SLEW=FAST"),
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Misc("VCCAUX_IO=NORMAL")
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),
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# DDR3 SDRAM near power supply
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("ddram", 1,
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Subsignal("a", Pins(
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"AG22 AJ23 AF22 AJ26 AG23 AD23 AF23 AJ24 AE23 AB23 AJ22 AK25 AD21 AD22 AK24"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("AK23 AF21 AC21"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("AF20"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("AK21"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("AJ21"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("AE21"), IOStandard("SSTL15")),
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Subsignal("dm", Pins(
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"AA28 AA27 AE28 AH30 AB18 AJ19 AD14 AK16"),
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IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"W29 Y29 AB30 AB29 W28 W26 Y28 AB28 AA25 AD27 AB24 AC24 Y26 Y25 AA26 AC26" + \
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"AD29 AE30 AE29 AF30 AD28 AC27 AF28 AF27 AG30 AG29 AH29 AJ29 AK30 AK29 AK28 AG27" + \
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"AD18 AD19 AA18 Y18 AE18 Y19 AB17 AA17 AH20 AH19 AG19 AF18 AJ18 AK18 AJ17 AJ16" + \
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"AF16 AE16 AE15 AF15 AC15 AB15 AC14 AB14 AH17 AH16 AK14 AJ14 AF17 AG17 AH15 AH14"),
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IOStandard("SSTL15_T_DCI")),
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Subsignal("dqs_p", Pins("Y30 AB25 AC29 AJ27 AC17 AK19 AC16 AG14"),
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IOStandard("DIFF_SSTL15")),
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Subsignal("dqs_n", Pins("AA30 AC25 AC30 AJ28 AD17 AK20 AD16 AG15"),
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IOStandard("DIFF_SSTL15")),
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Subsignal("clk_p", Pins("AA22"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("AA23"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("AB22"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("AH24"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("Y21"), IOStandard("LVCMOS15")),
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Misc("SLEW=FAST"),
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Misc("VCCAUX_IO=NORMAL")
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),
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# Sata
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("sata", 0,
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Subsignal("rx_p", Pins("C12")),
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Subsignal("rx_n", Pins("C11")),
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Subsignal("tx_p", Pins("A12")),
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Subsignal("tx_n", Pins("A11")),
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IOStandard("LVDS"),
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),
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("sata", 1,
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Subsignal("rx_p", Pins("E12")),
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Subsignal("rx_n", Pins("E11")),
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Subsignal("tx_p", Pins("B10")),
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Subsignal("tx_n", Pins("B9")),
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IOStandard("LVDS"),
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),
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# PCIe
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("pcie_x1", 0,
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Subsignal("rst_n", Pins("W21"), IOStandard("LVCMOS15")),
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Subsignal("clk_p", Pins("T6")),
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Subsignal("clk_n", Pins("T5")),
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Subsignal("rx_p", Pins("P6")),
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Subsignal("rx_n", Pins("P5")),
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Subsignal("tx_p", Pins("N4")),
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Subsignal("tx_n", Pins("N3"))
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),
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("pcie_x2", 0,
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Subsignal("rst_n", Pins("W21"), IOStandard("LVCMOS15")),
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Subsignal("clk_p", Pins("T6")),
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Subsignal("clk_n", Pins("T5")),
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Subsignal("rx_p", Pins("")),
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Subsignal("rx_p", Pins("P6 R4")),
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Subsignal("rx_n", Pins("P5 R3")),
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Subsignal("tx_p", Pins("N4 P2")),
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Subsignal("tx_n", Pins("N3 P1"))
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),
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("pcie_x4", 0,
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Subsignal("rst_n", Pins("W21"), IOStandard("LVCMOS15")),
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Subsignal("clk_p", Pins("T6")),
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Subsignal("clk_n", Pins("T5")),
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Subsignal("rx_p", Pins("P6 R4 U4 V6")),
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Subsignal("rx_n", Pins("P5 R3 U3 V5")),
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Subsignal("tx_p", Pins("N4 P2 T2 V2")),
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Subsignal("tx_n", Pins("N3 P1 T1 V1"))
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),
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("pcie_x8", 0,
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Subsignal("rst_n", Pins("W21"), IOStandard("LVCMOS33")),
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Subsignal("clk_p", Pins("T6")),
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Subsignal("clk_n", Pins("T5")),
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Subsignal("rx_p", Pins("P6 R4 U4 V6 W4 Y6 AA4 AB6")),
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Subsignal("rx_n", Pins("P5 R3 U3 V5 W3 Y5 AA3 AB5")),
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Subsignal("tx_p", Pins("N4 P2 T2 V2 Y2 AB2 AD2 AF2")),
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Subsignal("tx_n", Pins("N3 P1 T1 V1 Y1 AB1 AD1 AF1"))
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),
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# SFP
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("sfp_a", 0, # SFP A
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Subsignal("txp", Pins("A8")),
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Subsignal("txn", Pins("A7")),
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Subsignal("rxp", Pins("D10")),
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Subsignal("rxn", Pins("D9")),
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Subsignal("sda", Pins("C15")),
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Subsignal("scl", Pins("A15")),
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),
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("sfp_a_tx", 0, # SFP A
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Subsignal("p", Pins("A8")),
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Subsignal("n", Pins("A7"))
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),
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("sfp_a_rx", 0, # SFP A
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Subsignal("p", Pins("D10")),
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Subsignal("n", Pins("D9"))
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),
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("sfp_b", 0, # SFP B
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Subsignal("txp", Pins("C8")),
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Subsignal("txn", Pins("C7")),
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Subsignal("rxp", Pins("F10")),
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Subsignal("rxn", Pins("F9")),
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Subsignal("sda", Pins("C14")),
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Subsignal("scl", Pins("B14")),
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),
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("sfp_b_tx", 0, # SFP B
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Subsignal("p", Pins("C8")),
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Subsignal("n", Pins("C7"))
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),
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("sfp_b_rx", 0, # SFP B
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Subsignal("p", Pins("F10")),
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Subsignal("n", Pins("F9"))
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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#
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# Connector layout on the board
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# ┌────────────────────────────────────────┐
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# │ 2 80 │
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# │ ┌──────────────────────────────┐ │
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# └──┐ └──────────────────────────────┘ ┌──┘
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# │ 1 79 │
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# └──────────────────────────────────┘
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#
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_connectors = [
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# Connector on the SFP side
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("BTB_A", {
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# 1: "GND", 2: "GND",
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3: "A16", 4: "B24",
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5: "B17", 6: "D24",
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# 7: "GND", 8: "GND",
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9: "E16", 10: "A14",
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11: "F16", 12: "B15",
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13: "R25", 14: "U30",
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15: "R24", 16: "U29",
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# 17: "GND", 18: "GND",
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19: "R21", 20: "T27",
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21: "R20", 22: "R26",
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23: "T23", 24: "U28",
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25: "R23", 26: "U27",
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# 27: "GND", 28: "GND",
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29: "T18", 30: "V25",
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31: "T17", 32: "V24",
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33: "V20", 34: "R19",
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35: "U20", 36: "R18",
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# 37: "GND", 38: "GND",
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39: "W23", 40: "T21",
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41: "W22", 42: "T20",
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43: "U18", 44: "V19",
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45: "U17", 46: "U19",
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# 47: "GND", 48: "GND",
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49: "T26", 50: "W17",
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51: "T25", 52: "V17",
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53: "V22", 54: "W19",
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55: "V21", 56: "W18",
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# 57: "GND", 58: "GND",
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59: "C24", 60: "T22",
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61: "D26", 62: "V30",
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63: "C27", 64: "U25",
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65: "B27", 66: "AF25",
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# 67: "GND", 68: "GND"x
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69: "Y24", 70: "AH26",
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71: "AE26", 72: "AG25",
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73: "AD26", 74: "AH25",
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# 75: "GND", 76: "GND"
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# 77: "NC", 78: "3V3"
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# 79: "NC", 80: "3V3"
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}),
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# Connector on the power side
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("BTB_B", {
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# 1: "GND", 2: "GND",
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3: "AJ11", 4: "AK9",
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5: "AJ12", 6: "AK10",
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# 7: "GND", 8: "GND",
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9: "AJ7", 10: "AG11",
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11: "AJ8", 12: "AG12",
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# 13: "GND", 14: "GND",
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15: "AF9", 16: "AG7",
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17: "AF10", 18: "AG8",
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# 19: "GND", 20: "GND",
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21: "AE11", 22: "AH9",
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23: "AE12", 24: "AH10",
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# 25: "GND", 26: "GND",
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27: "AE8", 28: "AF6",
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29: "AE7", 30: "AF5",
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# 31: "GND", 32: "GND",
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33: "AG3", 34: "AK5",
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35: "AG4", 36: "AK6",
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# 37: "GND", 38: "GND",
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39: "AE3", 40: "AH5",
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41: "AE4", 42: "AH6",
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# 43: "GND", 44: "GND",
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45: "AK1", 46: "AJ3",
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47: "AK2", 48: "AJ4",
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# 49: "GND", 50: "GND",
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51: "AC3", 52: "AH1",
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53: "AC4", 54: "AH2",
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# 55: "GND", 56: "GND",
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58: "AC19",
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59: "L17", 60: "AB19",
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# 61: "GND", 62: "GND",
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63: "AC20", 64: "AB20",
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65: "AE20", 66: "AA20",
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# 67: "GND", 68: "GND",
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69: "W24", 70: "Y20",
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72: "AA21",
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# 73: "GND", 74: "GND",
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# 75: "NC", 76: "GND",
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# 77: "VCC12V", 78: "VCC3.3V",
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# 79: "VCC12V", 80: "VCC3.3V",
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}),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "diffclk100"
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default_clk_period = 1e9/100e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xc7k420t-ffg901-2", _io, _connectors, toolchain="ISE")
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self.add_platform_command("""
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property CFGBVS VCCO [current_design]
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""")
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self.toolchain.bitstream_commands = [
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"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
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"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]",
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"set_property BITSTREAM.CONFIG.CCLK_TRISTATE TRUE [current_design]",
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"set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]",
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"set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]",
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"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
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"set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]",
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"set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]",
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]
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self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 32 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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def create_programmer(self):
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return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a420t.bit")
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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self.add_period_constraint(self.lookup_request("diffclk100", loose=True), 1e9/100e6)
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@ -0,0 +1,163 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Andrew Gillham <gillham@roadsign.com>
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# Copyright (c) 2014-2015 Sebastien Bourdeauducq <sb@m-labs.hk>
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# Copyright (c) 2014-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2014-2015 Yann Sionneau <ys@m-labs.hk>
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# Copyright (c) 2020 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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# Board support for this chinese Kintex 420T board by "HPC FPGA Board Store"
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# https://www.aliexpress.com/item/1005001631827738.html
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import os
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from migen import *
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from litex_boards.platforms import aliexpress_stlv7325
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.bitbang import I2CMaster
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from litedram.modules import MT8JTF12864
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from litedram.phy import s7ddrphy
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from litepcie.phy.s7pciephy import S7PCIEPHY
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from litepcie.software import generate_litepcie_software
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
|
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self.clock_domains.cd_sys4x = ClockDomain()
|
||||
self.clock_domains.cd_idelay = ClockDomain()
|
||||
|
||||
# # #
|
||||
|
||||
# Clk/Rst.
|
||||
clk100 = platform.request("diffclk100")
|
||||
rst_n = platform.request("cpu_reset_n")
|
||||
|
||||
# PLL.
|
||||
self.submodules.pll = pll = S7MMCM(speedgrade=-2)
|
||||
self.comb += pll.reset.eq(~rst_n | self.rst)
|
||||
pll.register_clkin(clk100, 100e6)
|
||||
pll.create_clkout(self.cd_sys, sys_clk_freq)
|
||||
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
|
||||
pll.create_clkout(self.cd_idelay, 200e6)
|
||||
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
|
||||
|
||||
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
|
||||
|
||||
# BaseSoC ------------------------------------------------------------------------------------------
|
||||
|
||||
class BaseSoC(SoCCore):
|
||||
def __init__(self, sys_clk_freq=int(100e6),
|
||||
with_led_chaser = True,
|
||||
with_pcie = False,
|
||||
with_sata = False,
|
||||
**kwargs):
|
||||
platform = aliexpress_stlv7325.Platform()
|
||||
|
||||
# CRG --------------------------------------------------------------------------------------
|
||||
self.submodules.crg = _CRG(platform, sys_clk_freq)
|
||||
|
||||
# SoCCore ----------------------------------------------------------------------------------
|
||||
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on HPC Store XC7K420T", **kwargs)
|
||||
|
||||
# DDR3 SDRAM -------------------------------------------------------------------------------
|
||||
if not self.integrated_main_ram_size:
|
||||
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
|
||||
memtype = "DDR3",
|
||||
nphases = 4,
|
||||
sys_clk_freq = sys_clk_freq,
|
||||
)
|
||||
self.add_sdram("sdram",
|
||||
phy = self.ddrphy,
|
||||
module = MT8JTF12864(sys_clk_freq, "1:4"),
|
||||
l2_cache_size = kwargs.get("l2_size", 8192),
|
||||
)
|
||||
|
||||
# PCIe -------------------------------------------------------------------------------------
|
||||
if with_pcie:
|
||||
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
|
||||
data_width = 128,
|
||||
bar0_size = 0x20000)
|
||||
self.add_pcie(phy=self.pcie_phy, ndmas=1)
|
||||
|
||||
# TODO verify / test
|
||||
# SATA -------------------------------------------------------------------------------------
|
||||
if with_sata:
|
||||
from litex.build.generic_platform import Subsignal, Pins
|
||||
from litesata.phy import LiteSATAPHY
|
||||
|
||||
# RefClk, Generate 150MHz from PLL.
|
||||
self.clock_domains.cd_sata_refclk = ClockDomain()
|
||||
self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6)
|
||||
sata_refclk = ClockSignal("sata_refclk")
|
||||
platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]")
|
||||
|
||||
# PHY
|
||||
self.submodules.sata_phy = LiteSATAPHY(platform.device,
|
||||
refclk = sata_refclk,
|
||||
pads = platform.request("sata", 0),
|
||||
gen = "gen2",
|
||||
clk_freq = sys_clk_freq,
|
||||
data_width = 16)
|
||||
|
||||
# Core
|
||||
self.add_sata(phy=self.sata_phy, mode="read+write")
|
||||
|
||||
# Leds -------------------------------------------------------------------------------------
|
||||
if with_led_chaser:
|
||||
self.submodules.leds = LedChaser(
|
||||
pads = platform.request_all("user_led_n"),
|
||||
sys_clk_freq = sys_clk_freq)
|
||||
|
||||
# I2C --------------------------------------------------------------------------------------
|
||||
self.submodules.i2c = I2CMaster(platform.request("i2c"))
|
||||
|
||||
# Build --------------------------------------------------------------------------------------------
|
||||
|
||||
def main():
|
||||
from litex.soc.integration.soc import LiteXSoCArgumentParser
|
||||
parser = LiteXSoCArgumentParser(description="LiteX SoC on AliExpress HPC Store XC7K420T")
|
||||
target_group = parser.add_argument_group(title="Target options")
|
||||
target_group.add_argument("--build", action="store_true", help="Build design.")
|
||||
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
|
||||
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
|
||||
ethopts = target_group.add_mutually_exclusive_group()
|
||||
target_group.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
|
||||
target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
|
||||
target_group.add_argument("--with-sata", action="store_true", help="Enable SATA support.")
|
||||
builder_args(parser)
|
||||
soc_core_args(parser)
|
||||
args = parser.parse_args()
|
||||
|
||||
soc = BaseSoC(
|
||||
sys_clk_freq = int(float(args.sys_clk_freq)),
|
||||
with_pcie = args.with_pcie,
|
||||
with_sata = args.with_sata,
|
||||
**soc_core_argdict(args)
|
||||
)
|
||||
builder = Builder(soc, **builder_argdict(args))
|
||||
if args.build:
|
||||
builder.build()
|
||||
|
||||
if args.driver:
|
||||
generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
|
||||
|
||||
if args.load:
|
||||
prog = soc.platform.create_programmer()
|
||||
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
Loading…
Reference in New Issue